1/*
2 * Copyright (c) 2011 ARM Limited
| 1/*
2 * Copyright (c) 2011 ARM Limited
|
| 3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
|
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#ifndef __CPU_CHECKER_CPU_HH__
44#define __CPU_CHECKER_CPU_HH__
45
46#include <list>
47#include <map>
48#include <queue>
49
50#include "arch/types.hh"
51#include "base/statistics.hh"
52#include "cpu/base.hh"
53#include "cpu/base_dyn_inst.hh"
54#include "cpu/pc_event.hh"
55#include "cpu/simple_thread.hh"
56#include "cpu/static_inst.hh"
57#include "debug/Checker.hh"
58#include "params/CheckerCPU.hh"
59#include "sim/eventq.hh"
60
61// forward declarations
62namespace TheISA
63{
64 class TLB;
65}
66
67template <class>
68class BaseDynInst;
69class ThreadContext;
70class Request;
71
72/**
73 * CheckerCPU class. Dynamically verifies instructions as they are
74 * completed by making sure that the instruction and its results match
75 * the independent execution of the benchmark inside the checker. The
76 * checker verifies instructions in order, regardless of the order in
77 * which instructions complete. There are certain results that can
78 * not be verified, specifically the result of a store conditional or
79 * the values of uncached accesses. In these cases, and with
80 * instructions marked as "IsUnverifiable", the checker assumes that
81 * the value from the main CPU's execution is correct and simply
82 * copies that value. It provides a CheckerThreadContext (see
83 * checker/thread_context.hh) that provides hooks for updating the
84 * Checker's state through any ThreadContext accesses. This allows the
85 * checker to be able to correctly verify instructions, even with
86 * external accesses to the ThreadContext that change state.
87 */
88class CheckerCPU : public BaseCPU
89{
90 protected:
91 typedef TheISA::MachInst MachInst;
92 typedef TheISA::FloatReg FloatReg;
93 typedef TheISA::FloatRegBits FloatRegBits;
94 typedef TheISA::MiscReg MiscReg;
95
96 /** id attached to all issued requests */
97 MasterID masterId;
98 public:
99 virtual void init();
100
101 typedef CheckerCPUParams Params;
102 CheckerCPU(Params *p);
103 virtual ~CheckerCPU();
104
105 void setSystem(System *system);
106
107 void setIcachePort(MasterPort *icache_port);
108
109 void setDcachePort(MasterPort *dcache_port);
110
111 MasterPort &getDataPort()
112 {
113 // the checker does not have ports on its own so return the
114 // data port of the actual CPU core
115 assert(dcachePort);
116 return *dcachePort;
117 }
118
119 MasterPort &getInstPort()
120 {
121 // the checker does not have ports on its own so return the
122 // data port of the actual CPU core
123 assert(icachePort);
124 return *icachePort;
125 }
126
127 protected:
128
129 std::vector<Process*> workload;
130
131 System *systemPtr;
132
133 MasterPort *icachePort;
134 MasterPort *dcachePort;
135
136 ThreadContext *tc;
137
138 TheISA::TLB *itb;
139 TheISA::TLB *dtb;
140
141 Addr dbg_vtophys(Addr addr);
142
143 union Result {
144 uint64_t integer;
145 double dbl;
146 void set(uint64_t i) { integer = i; }
147 void set(double d) { dbl = d; }
148 void get(uint64_t& i) { i = integer; }
149 void get(double& d) { d = dbl; }
150 };
151
152 // ISAs like ARM can have multiple destination registers to check,
153 // keep them all in a std::queue
154 std::queue<Result> result;
155
156 // Pointer to the one memory request.
157 RequestPtr memReq;
158
159 StaticInstPtr curStaticInst;
160 StaticInstPtr curMacroStaticInst;
161
162 // number of simulated instructions
163 Counter numInst;
164 Counter startNumInst;
165
166 std::queue<int> miscRegIdxs;
167
168 public:
169
170 // Primary thread being run.
171 SimpleThread *thread;
172
173 TheISA::TLB* getITBPtr() { return itb; }
174 TheISA::TLB* getDTBPtr() { return dtb; }
175
176 virtual Counter totalInsts() const
177 {
178 return 0;
179 }
180
181 virtual Counter totalOps() const
182 {
183 return 0;
184 }
185
186 // number of simulated loads
187 Counter numLoad;
188 Counter startNumLoad;
189
190 virtual void serialize(std::ostream &os);
191 virtual void unserialize(Checkpoint *cp, const std::string §ion);
192
193 // These functions are only used in CPU models that split
194 // effective address computation from the actual memory access.
195 void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); }
196 Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); }
197
198 // The register accessor methods provide the index of the
199 // instruction's operand (e.g., 0 or 1), not the architectural
200 // register index, to simplify the implementation of register
201 // renaming. We find the architectural register index by indexing
202 // into the instruction's own operand index table. Note that a
203 // raw pointer to the StaticInst is provided instead of a
204 // ref-counted StaticInstPtr to redice overhead. This is fine as
205 // long as these methods don't copy the pointer into any long-term
206 // storage (which is pretty hard to imagine they would have reason
207 // to do).
208
209 uint64_t readIntRegOperand(const StaticInst *si, int idx)
210 {
211 return thread->readIntReg(si->srcRegIdx(idx));
212 }
213
214 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
215 {
216 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
217 return thread->readFloatReg(reg_idx);
218 }
219
220 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
221 {
222 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
223 return thread->readFloatRegBits(reg_idx);
224 }
225
| 4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_CHECKER_CPU_HH__
45#define __CPU_CHECKER_CPU_HH__
46
47#include <list>
48#include <map>
49#include <queue>
50
51#include "arch/types.hh"
52#include "base/statistics.hh"
53#include "cpu/base.hh"
54#include "cpu/base_dyn_inst.hh"
55#include "cpu/pc_event.hh"
56#include "cpu/simple_thread.hh"
57#include "cpu/static_inst.hh"
58#include "debug/Checker.hh"
59#include "params/CheckerCPU.hh"
60#include "sim/eventq.hh"
61
62// forward declarations
63namespace TheISA
64{
65 class TLB;
66}
67
68template <class>
69class BaseDynInst;
70class ThreadContext;
71class Request;
72
73/**
74 * CheckerCPU class. Dynamically verifies instructions as they are
75 * completed by making sure that the instruction and its results match
76 * the independent execution of the benchmark inside the checker. The
77 * checker verifies instructions in order, regardless of the order in
78 * which instructions complete. There are certain results that can
79 * not be verified, specifically the result of a store conditional or
80 * the values of uncached accesses. In these cases, and with
81 * instructions marked as "IsUnverifiable", the checker assumes that
82 * the value from the main CPU's execution is correct and simply
83 * copies that value. It provides a CheckerThreadContext (see
84 * checker/thread_context.hh) that provides hooks for updating the
85 * Checker's state through any ThreadContext accesses. This allows the
86 * checker to be able to correctly verify instructions, even with
87 * external accesses to the ThreadContext that change state.
88 */
89class CheckerCPU : public BaseCPU
90{
91 protected:
92 typedef TheISA::MachInst MachInst;
93 typedef TheISA::FloatReg FloatReg;
94 typedef TheISA::FloatRegBits FloatRegBits;
95 typedef TheISA::MiscReg MiscReg;
96
97 /** id attached to all issued requests */
98 MasterID masterId;
99 public:
100 virtual void init();
101
102 typedef CheckerCPUParams Params;
103 CheckerCPU(Params *p);
104 virtual ~CheckerCPU();
105
106 void setSystem(System *system);
107
108 void setIcachePort(MasterPort *icache_port);
109
110 void setDcachePort(MasterPort *dcache_port);
111
112 MasterPort &getDataPort()
113 {
114 // the checker does not have ports on its own so return the
115 // data port of the actual CPU core
116 assert(dcachePort);
117 return *dcachePort;
118 }
119
120 MasterPort &getInstPort()
121 {
122 // the checker does not have ports on its own so return the
123 // data port of the actual CPU core
124 assert(icachePort);
125 return *icachePort;
126 }
127
128 protected:
129
130 std::vector<Process*> workload;
131
132 System *systemPtr;
133
134 MasterPort *icachePort;
135 MasterPort *dcachePort;
136
137 ThreadContext *tc;
138
139 TheISA::TLB *itb;
140 TheISA::TLB *dtb;
141
142 Addr dbg_vtophys(Addr addr);
143
144 union Result {
145 uint64_t integer;
146 double dbl;
147 void set(uint64_t i) { integer = i; }
148 void set(double d) { dbl = d; }
149 void get(uint64_t& i) { i = integer; }
150 void get(double& d) { d = dbl; }
151 };
152
153 // ISAs like ARM can have multiple destination registers to check,
154 // keep them all in a std::queue
155 std::queue<Result> result;
156
157 // Pointer to the one memory request.
158 RequestPtr memReq;
159
160 StaticInstPtr curStaticInst;
161 StaticInstPtr curMacroStaticInst;
162
163 // number of simulated instructions
164 Counter numInst;
165 Counter startNumInst;
166
167 std::queue<int> miscRegIdxs;
168
169 public:
170
171 // Primary thread being run.
172 SimpleThread *thread;
173
174 TheISA::TLB* getITBPtr() { return itb; }
175 TheISA::TLB* getDTBPtr() { return dtb; }
176
177 virtual Counter totalInsts() const
178 {
179 return 0;
180 }
181
182 virtual Counter totalOps() const
183 {
184 return 0;
185 }
186
187 // number of simulated loads
188 Counter numLoad;
189 Counter startNumLoad;
190
191 virtual void serialize(std::ostream &os);
192 virtual void unserialize(Checkpoint *cp, const std::string §ion);
193
194 // These functions are only used in CPU models that split
195 // effective address computation from the actual memory access.
196 void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); }
197 Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); }
198
199 // The register accessor methods provide the index of the
200 // instruction's operand (e.g., 0 or 1), not the architectural
201 // register index, to simplify the implementation of register
202 // renaming. We find the architectural register index by indexing
203 // into the instruction's own operand index table. Note that a
204 // raw pointer to the StaticInst is provided instead of a
205 // ref-counted StaticInstPtr to redice overhead. This is fine as
206 // long as these methods don't copy the pointer into any long-term
207 // storage (which is pretty hard to imagine they would have reason
208 // to do).
209
210 uint64_t readIntRegOperand(const StaticInst *si, int idx)
211 {
212 return thread->readIntReg(si->srcRegIdx(idx));
213 }
214
215 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
216 {
217 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
218 return thread->readFloatReg(reg_idx);
219 }
220
221 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
222 {
223 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
224 return thread->readFloatRegBits(reg_idx);
225 }
226
|
| 227 uint64_t readCCRegOperand(const StaticInst *si, int idx)
228 {
229 int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
230 return thread->readCCReg(reg_idx);
231 }
232
|
226 template <class T>
227 void setResult(T t)
228 {
229 Result instRes;
230 instRes.set(t);
231 result.push(instRes);
232 }
233
234 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
235 {
236 thread->setIntReg(si->destRegIdx(idx), val);
237 setResult<uint64_t>(val);
238 }
239
240 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
241 {
242 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
243 thread->setFloatReg(reg_idx, val);
244 setResult<double>(val);
245 }
246
247 void setFloatRegOperandBits(const StaticInst *si, int idx,
248 FloatRegBits val)
249 {
250 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
251 thread->setFloatRegBits(reg_idx, val);
252 setResult<uint64_t>(val);
253 }
254
| 233 template <class T>
234 void setResult(T t)
235 {
236 Result instRes;
237 instRes.set(t);
238 result.push(instRes);
239 }
240
241 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
242 {
243 thread->setIntReg(si->destRegIdx(idx), val);
244 setResult<uint64_t>(val);
245 }
246
247 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
248 {
249 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
250 thread->setFloatReg(reg_idx, val);
251 setResult<double>(val);
252 }
253
254 void setFloatRegOperandBits(const StaticInst *si, int idx,
255 FloatRegBits val)
256 {
257 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
258 thread->setFloatRegBits(reg_idx, val);
259 setResult<uint64_t>(val);
260 }
261
|
| 262 void setCCRegOperand(const StaticInst *si, int idx, uint64_t val)
263 {
264 int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base;
265 thread->setCCReg(reg_idx, val);
266 setResult<uint64_t>(val);
267 }
268
|
255 bool readPredicate() { return thread->readPredicate(); }
256 void setPredicate(bool val)
257 {
258 thread->setPredicate(val);
259 }
260
261 TheISA::PCState pcState() { return thread->pcState(); }
262 void pcState(const TheISA::PCState &val)
263 {
264 DPRINTF(Checker, "Changing PC to %s, old PC %s.\n",
265 val, thread->pcState());
266 thread->pcState(val);
267 }
268 Addr instAddr() { return thread->instAddr(); }
269 Addr nextInstAddr() { return thread->nextInstAddr(); }
270 MicroPC microPC() { return thread->microPC(); }
271 //////////////////////////////////////////
272
273 MiscReg readMiscRegNoEffect(int misc_reg)
274 {
275 return thread->readMiscRegNoEffect(misc_reg);
276 }
277
278 MiscReg readMiscReg(int misc_reg)
279 {
280 return thread->readMiscReg(misc_reg);
281 }
282
283 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
284 {
285 miscRegIdxs.push(misc_reg);
286 return thread->setMiscRegNoEffect(misc_reg, val);
287 }
288
289 void setMiscReg(int misc_reg, const MiscReg &val)
290 {
291 miscRegIdxs.push(misc_reg);
292 return thread->setMiscReg(misc_reg, val);
293 }
294
295 MiscReg readMiscRegOperand(const StaticInst *si, int idx)
296 {
297 int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
298 return thread->readMiscReg(reg_idx);
299 }
300
301 void setMiscRegOperand(
302 const StaticInst *si, int idx, const MiscReg &val)
303 {
304 int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
305 return thread->setMiscReg(reg_idx, val);
306 }
307
308#if THE_ISA == MIPS_ISA
309 uint64_t readRegOtherThread(int misc_reg)
310 {
311 panic("MIPS MT not defined for CheckerCPU.\n");
312 return 0;
313 }
314
315 void setRegOtherThread(int misc_reg, const TheISA::MiscReg &val)
316 {
317 panic("MIPS MT not defined for CheckerCPU.\n");
318 }
319#endif
320
321 /////////////////////////////////////////
322
323 void recordPCChange(const TheISA::PCState &val)
324 {
325 changedPC = true;
326 newPCState = val;
327 }
328
329 void demapPage(Addr vaddr, uint64_t asn)
330 {
331 this->itb->demapPage(vaddr, asn);
332 this->dtb->demapPage(vaddr, asn);
333 }
334
335 void demapInstPage(Addr vaddr, uint64_t asn)
336 {
337 this->itb->demapPage(vaddr, asn);
338 }
339
340 void demapDataPage(Addr vaddr, uint64_t asn)
341 {
342 this->dtb->demapPage(vaddr, asn);
343 }
344
345 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
346 Fault writeMem(uint8_t *data, unsigned size,
347 Addr addr, unsigned flags, uint64_t *res);
348
349 void setStCondFailures(unsigned sc_failures)
350 {}
351 /////////////////////////////////////////////////////
352
353 Fault hwrei() { return thread->hwrei(); }
354 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
355 void wakeup() { }
356 // Assume that the normal CPU's call to syscall was successful.
357 // The checker's state would have already been updated by the syscall.
358 void syscall(uint64_t callnum) { }
359
360 void handleError()
361 {
362 if (exitOnError)
363 dumpAndExit();
364 }
365
366 bool checkFlags(Request *unverified_req, Addr vAddr,
367 Addr pAddr, int flags);
368
369 void dumpAndExit();
370
371 ThreadContext *tcBase() { return tc; }
372 SimpleThread *threadBase() { return thread; }
373
374 Result unverifiedResult;
375 Request *unverifiedReq;
376 uint8_t *unverifiedMemData;
377
378 bool changedPC;
379 bool willChangePC;
380 TheISA::PCState newPCState;
381 bool changedNextPC;
382 bool exitOnError;
383 bool updateOnError;
384 bool warnOnlyOnLoadError;
385
386 InstSeqNum youngestSN;
387};
388
389/**
390 * Templated Checker class. This Checker class is templated on the
391 * DynInstPtr of the instruction type that will be verified. Proper
392 * template instantiations of the Checker must be placed at the bottom
393 * of checker/cpu.cc.
394 */
395template <class Impl>
396class Checker : public CheckerCPU
397{
398 private:
399 typedef typename Impl::DynInstPtr DynInstPtr;
400
401 public:
402 Checker(Params *p)
403 : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL)
404 { }
405
406 void switchOut();
407 void takeOverFrom(BaseCPU *oldCPU);
408
409 void advancePC(Fault fault);
410
411 void verify(DynInstPtr &inst);
412
413 void validateInst(DynInstPtr &inst);
414 void validateExecution(DynInstPtr &inst);
415 void validateState();
416
417 void copyResult(DynInstPtr &inst, uint64_t mismatch_val, int start_idx);
418 void handlePendingInt();
419
420 private:
421 void handleError(DynInstPtr &inst)
422 {
423 if (exitOnError) {
424 dumpAndExit(inst);
425 } else if (updateOnError) {
426 updateThisCycle = true;
427 }
428 }
429
430 void dumpAndExit(DynInstPtr &inst);
431
432 bool updateThisCycle;
433
434 DynInstPtr unverifiedInst;
435
436 std::list<DynInstPtr> instList;
437 typedef typename std::list<DynInstPtr>::iterator InstListIt;
438 void dumpInsts();
439};
440
441#endif // __CPU_CHECKER_CPU_HH__
| 269 bool readPredicate() { return thread->readPredicate(); }
270 void setPredicate(bool val)
271 {
272 thread->setPredicate(val);
273 }
274
275 TheISA::PCState pcState() { return thread->pcState(); }
276 void pcState(const TheISA::PCState &val)
277 {
278 DPRINTF(Checker, "Changing PC to %s, old PC %s.\n",
279 val, thread->pcState());
280 thread->pcState(val);
281 }
282 Addr instAddr() { return thread->instAddr(); }
283 Addr nextInstAddr() { return thread->nextInstAddr(); }
284 MicroPC microPC() { return thread->microPC(); }
285 //////////////////////////////////////////
286
287 MiscReg readMiscRegNoEffect(int misc_reg)
288 {
289 return thread->readMiscRegNoEffect(misc_reg);
290 }
291
292 MiscReg readMiscReg(int misc_reg)
293 {
294 return thread->readMiscReg(misc_reg);
295 }
296
297 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
298 {
299 miscRegIdxs.push(misc_reg);
300 return thread->setMiscRegNoEffect(misc_reg, val);
301 }
302
303 void setMiscReg(int misc_reg, const MiscReg &val)
304 {
305 miscRegIdxs.push(misc_reg);
306 return thread->setMiscReg(misc_reg, val);
307 }
308
309 MiscReg readMiscRegOperand(const StaticInst *si, int idx)
310 {
311 int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
312 return thread->readMiscReg(reg_idx);
313 }
314
315 void setMiscRegOperand(
316 const StaticInst *si, int idx, const MiscReg &val)
317 {
318 int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
319 return thread->setMiscReg(reg_idx, val);
320 }
321
322#if THE_ISA == MIPS_ISA
323 uint64_t readRegOtherThread(int misc_reg)
324 {
325 panic("MIPS MT not defined for CheckerCPU.\n");
326 return 0;
327 }
328
329 void setRegOtherThread(int misc_reg, const TheISA::MiscReg &val)
330 {
331 panic("MIPS MT not defined for CheckerCPU.\n");
332 }
333#endif
334
335 /////////////////////////////////////////
336
337 void recordPCChange(const TheISA::PCState &val)
338 {
339 changedPC = true;
340 newPCState = val;
341 }
342
343 void demapPage(Addr vaddr, uint64_t asn)
344 {
345 this->itb->demapPage(vaddr, asn);
346 this->dtb->demapPage(vaddr, asn);
347 }
348
349 void demapInstPage(Addr vaddr, uint64_t asn)
350 {
351 this->itb->demapPage(vaddr, asn);
352 }
353
354 void demapDataPage(Addr vaddr, uint64_t asn)
355 {
356 this->dtb->demapPage(vaddr, asn);
357 }
358
359 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
360 Fault writeMem(uint8_t *data, unsigned size,
361 Addr addr, unsigned flags, uint64_t *res);
362
363 void setStCondFailures(unsigned sc_failures)
364 {}
365 /////////////////////////////////////////////////////
366
367 Fault hwrei() { return thread->hwrei(); }
368 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
369 void wakeup() { }
370 // Assume that the normal CPU's call to syscall was successful.
371 // The checker's state would have already been updated by the syscall.
372 void syscall(uint64_t callnum) { }
373
374 void handleError()
375 {
376 if (exitOnError)
377 dumpAndExit();
378 }
379
380 bool checkFlags(Request *unverified_req, Addr vAddr,
381 Addr pAddr, int flags);
382
383 void dumpAndExit();
384
385 ThreadContext *tcBase() { return tc; }
386 SimpleThread *threadBase() { return thread; }
387
388 Result unverifiedResult;
389 Request *unverifiedReq;
390 uint8_t *unverifiedMemData;
391
392 bool changedPC;
393 bool willChangePC;
394 TheISA::PCState newPCState;
395 bool changedNextPC;
396 bool exitOnError;
397 bool updateOnError;
398 bool warnOnlyOnLoadError;
399
400 InstSeqNum youngestSN;
401};
402
403/**
404 * Templated Checker class. This Checker class is templated on the
405 * DynInstPtr of the instruction type that will be verified. Proper
406 * template instantiations of the Checker must be placed at the bottom
407 * of checker/cpu.cc.
408 */
409template <class Impl>
410class Checker : public CheckerCPU
411{
412 private:
413 typedef typename Impl::DynInstPtr DynInstPtr;
414
415 public:
416 Checker(Params *p)
417 : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL)
418 { }
419
420 void switchOut();
421 void takeOverFrom(BaseCPU *oldCPU);
422
423 void advancePC(Fault fault);
424
425 void verify(DynInstPtr &inst);
426
427 void validateInst(DynInstPtr &inst);
428 void validateExecution(DynInstPtr &inst);
429 void validateState();
430
431 void copyResult(DynInstPtr &inst, uint64_t mismatch_val, int start_idx);
432 void handlePendingInt();
433
434 private:
435 void handleError(DynInstPtr &inst)
436 {
437 if (exitOnError) {
438 dumpAndExit(inst);
439 } else if (updateOnError) {
440 updateThisCycle = true;
441 }
442 }
443
444 void dumpAndExit(DynInstPtr &inst);
445
446 bool updateThisCycle;
447
448 DynInstPtr unverifiedInst;
449
450 std::list<DynInstPtr> instList;
451 typedef typename std::list<DynInstPtr>::iterator InstListIt;
452 void dumpInsts();
453};
454
455#endif // __CPU_CHECKER_CPU_HH__
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