1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#ifndef __CPU_CHECKER_CPU_HH__
44#define __CPU_CHECKER_CPU_HH__
45
46#include <list>
47#include <map>
48#include <queue>
49
50#include "arch/predecoder.hh"
51#include "arch/types.hh"
52#include "base/statistics.hh"
53#include "cpu/base.hh"
54#include "cpu/base_dyn_inst.hh"
55#include "cpu/pc_event.hh"
56#include "cpu/simple_thread.hh"
57#include "cpu/static_inst.hh"
58#include "debug/Checker.hh"
59#include "params/CheckerCPU.hh"
60#include "sim/eventq.hh"
61
62// forward declarations
63namespace TheISA
64{
65 class TLB;
66}
67
68template <class>
69class BaseDynInst;
70class ThreadContext;
71class Request;
72
73/**
74 * CheckerCPU class. Dynamically verifies instructions as they are
75 * completed by making sure that the instruction and its results match
76 * the independent execution of the benchmark inside the checker. The
77 * checker verifies instructions in order, regardless of the order in
78 * which instructions complete. There are certain results that can
79 * not be verified, specifically the result of a store conditional or
80 * the values of uncached accesses. In these cases, and with
81 * instructions marked as "IsUnverifiable", the checker assumes that
82 * the value from the main CPU's execution is correct and simply
83 * copies that value. It provides a CheckerThreadContext (see
84 * checker/thread_context.hh) that provides hooks for updating the
85 * Checker's state through any ThreadContext accesses. This allows the
86 * checker to be able to correctly verify instructions, even with
87 * external accesses to the ThreadContext that change state.
88 */
89class CheckerCPU : public BaseCPU
90{
91 protected:
92 typedef TheISA::MachInst MachInst;
93 typedef TheISA::FloatReg FloatReg;
94 typedef TheISA::FloatRegBits FloatRegBits;
95 typedef TheISA::MiscReg MiscReg;
| 1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#ifndef __CPU_CHECKER_CPU_HH__
44#define __CPU_CHECKER_CPU_HH__
45
46#include <list>
47#include <map>
48#include <queue>
49
50#include "arch/predecoder.hh"
51#include "arch/types.hh"
52#include "base/statistics.hh"
53#include "cpu/base.hh"
54#include "cpu/base_dyn_inst.hh"
55#include "cpu/pc_event.hh"
56#include "cpu/simple_thread.hh"
57#include "cpu/static_inst.hh"
58#include "debug/Checker.hh"
59#include "params/CheckerCPU.hh"
60#include "sim/eventq.hh"
61
62// forward declarations
63namespace TheISA
64{
65 class TLB;
66}
67
68template <class>
69class BaseDynInst;
70class ThreadContext;
71class Request;
72
73/**
74 * CheckerCPU class. Dynamically verifies instructions as they are
75 * completed by making sure that the instruction and its results match
76 * the independent execution of the benchmark inside the checker. The
77 * checker verifies instructions in order, regardless of the order in
78 * which instructions complete. There are certain results that can
79 * not be verified, specifically the result of a store conditional or
80 * the values of uncached accesses. In these cases, and with
81 * instructions marked as "IsUnverifiable", the checker assumes that
82 * the value from the main CPU's execution is correct and simply
83 * copies that value. It provides a CheckerThreadContext (see
84 * checker/thread_context.hh) that provides hooks for updating the
85 * Checker's state through any ThreadContext accesses. This allows the
86 * checker to be able to correctly verify instructions, even with
87 * external accesses to the ThreadContext that change state.
88 */
89class CheckerCPU : public BaseCPU
90{
91 protected:
92 typedef TheISA::MachInst MachInst;
93 typedef TheISA::FloatReg FloatReg;
94 typedef TheISA::FloatRegBits FloatRegBits;
95 typedef TheISA::MiscReg MiscReg;
|
96 public:
97 virtual void init();
98
99 public:
100 typedef CheckerCPUParams Params;
101 const Params *params() const
102 { return reinterpret_cast<const Params *>(_params); }
103 CheckerCPU(Params *p);
104 virtual ~CheckerCPU();
105
106 std::vector<Process*> workload;
107
108 void setSystem(System *system);
109
110 System *systemPtr;
111
112 void setIcachePort(Port *icache_port);
113
114 Port *icachePort;
115
116 void setDcachePort(Port *dcache_port);
117
118 Port *dcachePort;
119
120 virtual Port *getPort(const std::string &name, int idx)
121 {
122 panic("Not supported on checker!");
123 return NULL;
124 }
125
126 public:
127 // Primary thread being run.
128 SimpleThread *thread;
129
130 ThreadContext *tc;
131
132 TheISA::TLB *itb;
133 TheISA::TLB *dtb;
134
135 Addr dbg_vtophys(Addr addr);
136
137 union Result {
138 uint64_t integer;
139 double dbl;
140 void set(uint64_t i) { integer = i; }
141 void set(double d) { dbl = d; }
142 void get(uint64_t& i) { i = integer; }
143 void get(double& d) { d = dbl; }
144 };
145
146 // ISAs like ARM can have multiple destination registers to check,
147 // keep them all in a std::queue
148 std::queue<Result> result;
149
150 // current instruction
151 TheISA::MachInst machInst;
152
153 // Pointer to the one memory request.
154 RequestPtr memReq;
155
156 StaticInstPtr curStaticInst;
157 StaticInstPtr curMacroStaticInst;
158
159 // number of simulated instructions
160 Counter numInst;
161 Counter startNumInst;
162
163 std::queue<int> miscRegIdxs;
164
165 TheISA::TLB* getITBPtr() { return itb; }
166 TheISA::TLB* getDTBPtr() { return dtb; }
167
168 virtual Counter totalInstructions() const
169 {
170 return 0;
171 }
172
173 // number of simulated loads
174 Counter numLoad;
175 Counter startNumLoad;
176
177 virtual void serialize(std::ostream &os);
178 virtual void unserialize(Checkpoint *cp, const std::string §ion);
179
180 // These functions are only used in CPU models that split
181 // effective address computation from the actual memory access.
182 void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); }
183 Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); }
184
185 // The register accessor methods provide the index of the
186 // instruction's operand (e.g., 0 or 1), not the architectural
187 // register index, to simplify the implementation of register
188 // renaming. We find the architectural register index by indexing
189 // into the instruction's own operand index table. Note that a
190 // raw pointer to the StaticInst is provided instead of a
191 // ref-counted StaticInstPtr to redice overhead. This is fine as
192 // long as these methods don't copy the pointer into any long-term
193 // storage (which is pretty hard to imagine they would have reason
194 // to do).
195
196 uint64_t readIntRegOperand(const StaticInst *si, int idx)
197 {
198 return thread->readIntReg(si->srcRegIdx(idx));
199 }
200
201 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
202 {
203 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
204 return thread->readFloatReg(reg_idx);
205 }
206
207 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
208 {
209 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
210 return thread->readFloatRegBits(reg_idx);
211 }
212
213 template <class T>
214 void setResult(T t)
215 {
216 Result instRes;
217 instRes.set(t);
218 result.push(instRes);
219 }
220
221 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
222 {
223 thread->setIntReg(si->destRegIdx(idx), val);
224 setResult<uint64_t>(val);
225 }
226
227 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
228 {
229 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
230 thread->setFloatReg(reg_idx, val);
231 setResult<double>(val);
232 }
233
234 void setFloatRegOperandBits(const StaticInst *si, int idx,
235 FloatRegBits val)
236 {
237 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
238 thread->setFloatRegBits(reg_idx, val);
239 setResult<uint64_t>(val);
240 }
241
242 bool readPredicate() { return thread->readPredicate(); }
243 void setPredicate(bool val)
244 {
245 thread->setPredicate(val);
246 }
247
248 TheISA::PCState pcState() { return thread->pcState(); }
249 void pcState(const TheISA::PCState &val)
250 {
251 DPRINTF(Checker, "Changing PC to %s, old PC %s.\n",
252 val, thread->pcState());
253 thread->pcState(val);
254 }
255 Addr instAddr() { return thread->instAddr(); }
256 Addr nextInstAddr() { return thread->nextInstAddr(); }
257 MicroPC microPC() { return thread->microPC(); }
258 //////////////////////////////////////////
259
260 MiscReg readMiscRegNoEffect(int misc_reg)
261 {
262 return thread->readMiscRegNoEffect(misc_reg);
263 }
264
265 MiscReg readMiscReg(int misc_reg)
266 {
267 return thread->readMiscReg(misc_reg);
268 }
269
270 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
271 {
272 miscRegIdxs.push(misc_reg);
273 return thread->setMiscRegNoEffect(misc_reg, val);
274 }
275
276 void setMiscReg(int misc_reg, const MiscReg &val)
277 {
278 miscRegIdxs.push(misc_reg);
279 return thread->setMiscReg(misc_reg, val);
280 }
281
282 MiscReg readMiscRegOperand(const StaticInst *si, int idx)
283 {
284 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
285 return thread->readMiscReg(reg_idx);
286 }
287
288 void setMiscRegOperand(
289 const StaticInst *si, int idx, const MiscReg &val)
290 {
291 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
292 return thread->setMiscReg(reg_idx, val);
293 }
294 /////////////////////////////////////////
295
296 void recordPCChange(const TheISA::PCState &val)
297 {
298 changedPC = true;
299 newPCState = val;
300 }
301
302 void demapPage(Addr vaddr, uint64_t asn)
303 {
304 this->itb->demapPage(vaddr, asn);
305 this->dtb->demapPage(vaddr, asn);
306 }
307
308 void demapInstPage(Addr vaddr, uint64_t asn)
309 {
310 this->itb->demapPage(vaddr, asn);
311 }
312
313 void demapDataPage(Addr vaddr, uint64_t asn)
314 {
315 this->dtb->demapPage(vaddr, asn);
316 }
317
318 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
319 Fault writeMem(uint8_t *data, unsigned size,
320 Addr addr, unsigned flags, uint64_t *res);
321
322 void setStCondFailures(unsigned sc_failures)
323 {}
324 /////////////////////////////////////////////////////
325
326 Fault hwrei() { return thread->hwrei(); }
327 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
328 void wakeup() { }
329 // Assume that the normal CPU's call to syscall was successful.
330 // The checker's state would have already been updated by the syscall.
331 void syscall(uint64_t callnum) { }
332
333 void handleError()
334 {
335 if (exitOnError)
336 dumpAndExit();
337 }
338
339 bool checkFlags(Request *unverified_req, Addr vAddr,
340 Addr pAddr, int flags);
341
342 void dumpAndExit();
343
344 ThreadContext *tcBase() { return tc; }
345 SimpleThread *threadBase() { return thread; }
346
347 Result unverifiedResult;
348 Request *unverifiedReq;
349 uint8_t *unverifiedMemData;
350
351 bool changedPC;
352 bool willChangePC;
353 TheISA::PCState newPCState;
354 bool changedNextPC;
355 bool exitOnError;
356 bool updateOnError;
357 bool warnOnlyOnLoadError;
358
359 InstSeqNum youngestSN;
360};
361
362/**
363 * Templated Checker class. This Checker class is templated on the
364 * DynInstPtr of the instruction type that will be verified. Proper
365 * template instantiations of the Checker must be placed at the bottom
366 * of checker/cpu.cc.
367 */
368template <class Impl>
369class Checker : public CheckerCPU
370{
371 private:
372 typedef typename Impl::DynInstPtr DynInstPtr;
373
374 public:
375 Checker(Params *p)
376 : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL),
377 predecoder(NULL)
378 { }
379
380 void switchOut();
381 void takeOverFrom(BaseCPU *oldCPU);
382
383 void advancePC(Fault fault);
384
385 void verify(DynInstPtr &inst);
386
387 void validateInst(DynInstPtr &inst);
388 void validateExecution(DynInstPtr &inst);
389 void validateState();
390
391 void copyResult(DynInstPtr &inst, uint64_t mismatch_val, int start_idx);
392 void handlePendingInt();
393
394 private:
395 void handleError(DynInstPtr &inst)
396 {
397 if (exitOnError) {
398 dumpAndExit(inst);
399 } else if (updateOnError) {
400 updateThisCycle = true;
401 }
402 }
403
404 void dumpAndExit(DynInstPtr &inst);
405
406 bool updateThisCycle;
407
408 DynInstPtr unverifiedInst;
409 TheISA::Predecoder predecoder;
410
411 std::list<DynInstPtr> instList;
412 typedef typename std::list<DynInstPtr>::iterator InstListIt;
413 void dumpInsts();
414};
415
416#endif // __CPU_CHECKER_CPU_HH__
| 99 public:
100 virtual void init();
101
102 public:
103 typedef CheckerCPUParams Params;
104 const Params *params() const
105 { return reinterpret_cast<const Params *>(_params); }
106 CheckerCPU(Params *p);
107 virtual ~CheckerCPU();
108
109 std::vector<Process*> workload;
110
111 void setSystem(System *system);
112
113 System *systemPtr;
114
115 void setIcachePort(Port *icache_port);
116
117 Port *icachePort;
118
119 void setDcachePort(Port *dcache_port);
120
121 Port *dcachePort;
122
123 virtual Port *getPort(const std::string &name, int idx)
124 {
125 panic("Not supported on checker!");
126 return NULL;
127 }
128
129 public:
130 // Primary thread being run.
131 SimpleThread *thread;
132
133 ThreadContext *tc;
134
135 TheISA::TLB *itb;
136 TheISA::TLB *dtb;
137
138 Addr dbg_vtophys(Addr addr);
139
140 union Result {
141 uint64_t integer;
142 double dbl;
143 void set(uint64_t i) { integer = i; }
144 void set(double d) { dbl = d; }
145 void get(uint64_t& i) { i = integer; }
146 void get(double& d) { d = dbl; }
147 };
148
149 // ISAs like ARM can have multiple destination registers to check,
150 // keep them all in a std::queue
151 std::queue<Result> result;
152
153 // current instruction
154 TheISA::MachInst machInst;
155
156 // Pointer to the one memory request.
157 RequestPtr memReq;
158
159 StaticInstPtr curStaticInst;
160 StaticInstPtr curMacroStaticInst;
161
162 // number of simulated instructions
163 Counter numInst;
164 Counter startNumInst;
165
166 std::queue<int> miscRegIdxs;
167
168 TheISA::TLB* getITBPtr() { return itb; }
169 TheISA::TLB* getDTBPtr() { return dtb; }
170
171 virtual Counter totalInstructions() const
172 {
173 return 0;
174 }
175
176 // number of simulated loads
177 Counter numLoad;
178 Counter startNumLoad;
179
180 virtual void serialize(std::ostream &os);
181 virtual void unserialize(Checkpoint *cp, const std::string §ion);
182
183 // These functions are only used in CPU models that split
184 // effective address computation from the actual memory access.
185 void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); }
186 Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); }
187
188 // The register accessor methods provide the index of the
189 // instruction's operand (e.g., 0 or 1), not the architectural
190 // register index, to simplify the implementation of register
191 // renaming. We find the architectural register index by indexing
192 // into the instruction's own operand index table. Note that a
193 // raw pointer to the StaticInst is provided instead of a
194 // ref-counted StaticInstPtr to redice overhead. This is fine as
195 // long as these methods don't copy the pointer into any long-term
196 // storage (which is pretty hard to imagine they would have reason
197 // to do).
198
199 uint64_t readIntRegOperand(const StaticInst *si, int idx)
200 {
201 return thread->readIntReg(si->srcRegIdx(idx));
202 }
203
204 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
205 {
206 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
207 return thread->readFloatReg(reg_idx);
208 }
209
210 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
211 {
212 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
213 return thread->readFloatRegBits(reg_idx);
214 }
215
216 template <class T>
217 void setResult(T t)
218 {
219 Result instRes;
220 instRes.set(t);
221 result.push(instRes);
222 }
223
224 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
225 {
226 thread->setIntReg(si->destRegIdx(idx), val);
227 setResult<uint64_t>(val);
228 }
229
230 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
231 {
232 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
233 thread->setFloatReg(reg_idx, val);
234 setResult<double>(val);
235 }
236
237 void setFloatRegOperandBits(const StaticInst *si, int idx,
238 FloatRegBits val)
239 {
240 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
241 thread->setFloatRegBits(reg_idx, val);
242 setResult<uint64_t>(val);
243 }
244
245 bool readPredicate() { return thread->readPredicate(); }
246 void setPredicate(bool val)
247 {
248 thread->setPredicate(val);
249 }
250
251 TheISA::PCState pcState() { return thread->pcState(); }
252 void pcState(const TheISA::PCState &val)
253 {
254 DPRINTF(Checker, "Changing PC to %s, old PC %s.\n",
255 val, thread->pcState());
256 thread->pcState(val);
257 }
258 Addr instAddr() { return thread->instAddr(); }
259 Addr nextInstAddr() { return thread->nextInstAddr(); }
260 MicroPC microPC() { return thread->microPC(); }
261 //////////////////////////////////////////
262
263 MiscReg readMiscRegNoEffect(int misc_reg)
264 {
265 return thread->readMiscRegNoEffect(misc_reg);
266 }
267
268 MiscReg readMiscReg(int misc_reg)
269 {
270 return thread->readMiscReg(misc_reg);
271 }
272
273 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
274 {
275 miscRegIdxs.push(misc_reg);
276 return thread->setMiscRegNoEffect(misc_reg, val);
277 }
278
279 void setMiscReg(int misc_reg, const MiscReg &val)
280 {
281 miscRegIdxs.push(misc_reg);
282 return thread->setMiscReg(misc_reg, val);
283 }
284
285 MiscReg readMiscRegOperand(const StaticInst *si, int idx)
286 {
287 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
288 return thread->readMiscReg(reg_idx);
289 }
290
291 void setMiscRegOperand(
292 const StaticInst *si, int idx, const MiscReg &val)
293 {
294 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
295 return thread->setMiscReg(reg_idx, val);
296 }
297 /////////////////////////////////////////
298
299 void recordPCChange(const TheISA::PCState &val)
300 {
301 changedPC = true;
302 newPCState = val;
303 }
304
305 void demapPage(Addr vaddr, uint64_t asn)
306 {
307 this->itb->demapPage(vaddr, asn);
308 this->dtb->demapPage(vaddr, asn);
309 }
310
311 void demapInstPage(Addr vaddr, uint64_t asn)
312 {
313 this->itb->demapPage(vaddr, asn);
314 }
315
316 void demapDataPage(Addr vaddr, uint64_t asn)
317 {
318 this->dtb->demapPage(vaddr, asn);
319 }
320
321 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
322 Fault writeMem(uint8_t *data, unsigned size,
323 Addr addr, unsigned flags, uint64_t *res);
324
325 void setStCondFailures(unsigned sc_failures)
326 {}
327 /////////////////////////////////////////////////////
328
329 Fault hwrei() { return thread->hwrei(); }
330 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
331 void wakeup() { }
332 // Assume that the normal CPU's call to syscall was successful.
333 // The checker's state would have already been updated by the syscall.
334 void syscall(uint64_t callnum) { }
335
336 void handleError()
337 {
338 if (exitOnError)
339 dumpAndExit();
340 }
341
342 bool checkFlags(Request *unverified_req, Addr vAddr,
343 Addr pAddr, int flags);
344
345 void dumpAndExit();
346
347 ThreadContext *tcBase() { return tc; }
348 SimpleThread *threadBase() { return thread; }
349
350 Result unverifiedResult;
351 Request *unverifiedReq;
352 uint8_t *unverifiedMemData;
353
354 bool changedPC;
355 bool willChangePC;
356 TheISA::PCState newPCState;
357 bool changedNextPC;
358 bool exitOnError;
359 bool updateOnError;
360 bool warnOnlyOnLoadError;
361
362 InstSeqNum youngestSN;
363};
364
365/**
366 * Templated Checker class. This Checker class is templated on the
367 * DynInstPtr of the instruction type that will be verified. Proper
368 * template instantiations of the Checker must be placed at the bottom
369 * of checker/cpu.cc.
370 */
371template <class Impl>
372class Checker : public CheckerCPU
373{
374 private:
375 typedef typename Impl::DynInstPtr DynInstPtr;
376
377 public:
378 Checker(Params *p)
379 : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL),
380 predecoder(NULL)
381 { }
382
383 void switchOut();
384 void takeOverFrom(BaseCPU *oldCPU);
385
386 void advancePC(Fault fault);
387
388 void verify(DynInstPtr &inst);
389
390 void validateInst(DynInstPtr &inst);
391 void validateExecution(DynInstPtr &inst);
392 void validateState();
393
394 void copyResult(DynInstPtr &inst, uint64_t mismatch_val, int start_idx);
395 void handlePendingInt();
396
397 private:
398 void handleError(DynInstPtr &inst)
399 {
400 if (exitOnError) {
401 dumpAndExit(inst);
402 } else if (updateOnError) {
403 updateThisCycle = true;
404 }
405 }
406
407 void dumpAndExit(DynInstPtr &inst);
408
409 bool updateThisCycle;
410
411 DynInstPtr unverifiedInst;
412 TheISA::Predecoder predecoder;
413
414 std::list<DynInstPtr> instList;
415 typedef typename std::list<DynInstPtr>::iterator InstListIt;
416 void dumpInsts();
417};
418
419#endif // __CPU_CHECKER_CPU_HH__
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