1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_CHECKER_CPU_HH__
32#define __CPU_CHECKER_CPU_HH__
33
34#include <list>
35#include <queue>
36#include <map>
37
38#include "arch/types.hh"
39#include "base/statistics.hh"
40#include "config/full_system.hh"
41#include "cpu/base.hh"
42#include "cpu/base_dyn_inst.hh"
43#include "cpu/simple_thread.hh"
44#include "cpu/pc_event.hh"
45#include "cpu/static_inst.hh"
46#include "sim/eventq.hh"
47
48// forward declarations
49#if FULL_SYSTEM
| 1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_CHECKER_CPU_HH__
32#define __CPU_CHECKER_CPU_HH__
33
34#include <list>
35#include <queue>
36#include <map>
37
38#include "arch/types.hh"
39#include "base/statistics.hh"
40#include "config/full_system.hh"
41#include "cpu/base.hh"
42#include "cpu/base_dyn_inst.hh"
43#include "cpu/simple_thread.hh"
44#include "cpu/pc_event.hh"
45#include "cpu/static_inst.hh"
46#include "sim/eventq.hh"
47
48// forward declarations
49#if FULL_SYSTEM
|
| 50namespace TheISA
51{
52 class ITB;
53 class DTB;
54}
|
50class Processor;
| 55class Processor;
|
51class AlphaITB;
52class AlphaDTB;
| |
53class PhysicalMemory;
54
55class RemoteGDB;
56class GDBListener;
57
58#else
59
60class Process;
61
62#endif // FULL_SYSTEM
63template <class>
64class BaseDynInst;
65class ThreadContext;
66class MemInterface;
67class Checkpoint;
68class Request;
69
70/**
71 * CheckerCPU class. Dynamically verifies instructions as they are
72 * completed by making sure that the instruction and its results match
73 * the independent execution of the benchmark inside the checker. The
74 * checker verifies instructions in order, regardless of the order in
75 * which instructions complete. There are certain results that can
76 * not be verified, specifically the result of a store conditional or
77 * the values of uncached accesses. In these cases, and with
78 * instructions marked as "IsUnverifiable", the checker assumes that
79 * the value from the main CPU's execution is correct and simply
80 * copies that value. It provides a CheckerThreadContext (see
81 * checker/thread_context.hh) that provides hooks for updating the
82 * Checker's state through any ThreadContext accesses. This allows the
83 * checker to be able to correctly verify instructions, even with
84 * external accesses to the ThreadContext that change state.
85 */
86class CheckerCPU : public BaseCPU
87{
88 protected:
89 typedef TheISA::MachInst MachInst;
90 typedef TheISA::FloatReg FloatReg;
91 typedef TheISA::FloatRegBits FloatRegBits;
92 typedef TheISA::MiscReg MiscReg;
93 public:
94 virtual void init();
95
96 struct Params : public BaseCPU::Params
97 {
98#if FULL_SYSTEM
| 56class PhysicalMemory;
57
58class RemoteGDB;
59class GDBListener;
60
61#else
62
63class Process;
64
65#endif // FULL_SYSTEM
66template <class>
67class BaseDynInst;
68class ThreadContext;
69class MemInterface;
70class Checkpoint;
71class Request;
72
73/**
74 * CheckerCPU class. Dynamically verifies instructions as they are
75 * completed by making sure that the instruction and its results match
76 * the independent execution of the benchmark inside the checker. The
77 * checker verifies instructions in order, regardless of the order in
78 * which instructions complete. There are certain results that can
79 * not be verified, specifically the result of a store conditional or
80 * the values of uncached accesses. In these cases, and with
81 * instructions marked as "IsUnverifiable", the checker assumes that
82 * the value from the main CPU's execution is correct and simply
83 * copies that value. It provides a CheckerThreadContext (see
84 * checker/thread_context.hh) that provides hooks for updating the
85 * Checker's state through any ThreadContext accesses. This allows the
86 * checker to be able to correctly verify instructions, even with
87 * external accesses to the ThreadContext that change state.
88 */
89class CheckerCPU : public BaseCPU
90{
91 protected:
92 typedef TheISA::MachInst MachInst;
93 typedef TheISA::FloatReg FloatReg;
94 typedef TheISA::FloatRegBits FloatRegBits;
95 typedef TheISA::MiscReg MiscReg;
96 public:
97 virtual void init();
98
99 struct Params : public BaseCPU::Params
100 {
101#if FULL_SYSTEM
|
99 AlphaITB *itb;
100 AlphaDTB *dtb;
| 102 TheISA::ITB *itb;
103 TheISA::DTB *dtb;
|
101#else
102 Process *process;
103#endif
104 bool exitOnError;
105 bool updateOnError;
106 bool warnOnlyOnLoadError;
107 };
108
109 public:
110 CheckerCPU(Params *p);
111 virtual ~CheckerCPU();
112
113 Process *process;
114
115 void setMemory(MemObject *mem);
116
117 MemObject *memPtr;
118
119 void setSystem(System *system);
120
121 System *systemPtr;
122
123 void setIcachePort(Port *icache_port);
124
125 Port *icachePort;
126
127 void setDcachePort(Port *dcache_port);
128
129 Port *dcachePort;
130
131 virtual Port *getPort(const std::string &name, int idx)
132 {
133 panic("Not supported on checker!");
134 return NULL;
135 }
136
137 public:
138 // Primary thread being run.
139 SimpleThread *thread;
140
141 ThreadContext *tc;
142
| 104#else
105 Process *process;
106#endif
107 bool exitOnError;
108 bool updateOnError;
109 bool warnOnlyOnLoadError;
110 };
111
112 public:
113 CheckerCPU(Params *p);
114 virtual ~CheckerCPU();
115
116 Process *process;
117
118 void setMemory(MemObject *mem);
119
120 MemObject *memPtr;
121
122 void setSystem(System *system);
123
124 System *systemPtr;
125
126 void setIcachePort(Port *icache_port);
127
128 Port *icachePort;
129
130 void setDcachePort(Port *dcache_port);
131
132 Port *dcachePort;
133
134 virtual Port *getPort(const std::string &name, int idx)
135 {
136 panic("Not supported on checker!");
137 return NULL;
138 }
139
140 public:
141 // Primary thread being run.
142 SimpleThread *thread;
143
144 ThreadContext *tc;
145
|
143 AlphaITB *itb;
144 AlphaDTB *dtb;
| 146 TheISA::ITB *itb;
147 TheISA::DTB *dtb;
|
145
146#if FULL_SYSTEM
147 Addr dbg_vtophys(Addr addr);
148#endif
149
150 union Result {
151 uint64_t integer;
152// float fp;
153 double dbl;
154 };
155
156 Result result;
157
158 // current instruction
159 MachInst machInst;
160
161 // Pointer to the one memory request.
162 RequestPtr memReq;
163
164 StaticInstPtr curStaticInst;
165
166 // number of simulated instructions
167 Counter numInst;
168 Counter startNumInst;
169
170 std::queue<int> miscRegIdxs;
171
172 virtual Counter totalInstructions() const
173 {
174 return 0;
175 }
176
177 // number of simulated loads
178 Counter numLoad;
179 Counter startNumLoad;
180
181 virtual void serialize(std::ostream &os);
182 virtual void unserialize(Checkpoint *cp, const std::string §ion);
183
184 template <class T>
185 Fault read(Addr addr, T &data, unsigned flags);
186
187 template <class T>
188 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
189
190 // These functions are only used in CPU models that split
191 // effective address computation from the actual memory access.
192 void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); }
193 Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); }
194
195 void prefetch(Addr addr, unsigned flags)
196 {
197 // need to do this...
198 }
199
200 void writeHint(Addr addr, int size, unsigned flags)
201 {
202 // need to do this...
203 }
204
205 Fault copySrcTranslate(Addr src);
206
207 Fault copy(Addr dest);
208
209 // The register accessor methods provide the index of the
210 // instruction's operand (e.g., 0 or 1), not the architectural
211 // register index, to simplify the implementation of register
212 // renaming. We find the architectural register index by indexing
213 // into the instruction's own operand index table. Note that a
214 // raw pointer to the StaticInst is provided instead of a
215 // ref-counted StaticInstPtr to redice overhead. This is fine as
216 // long as these methods don't copy the pointer into any long-term
217 // storage (which is pretty hard to imagine they would have reason
218 // to do).
219
220 uint64_t readIntReg(const StaticInst *si, int idx)
221 {
222 return thread->readIntReg(si->srcRegIdx(idx));
223 }
224
225 FloatReg readFloatReg(const StaticInst *si, int idx, int width)
226 {
227 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
228 return thread->readFloatReg(reg_idx, width);
229 }
230
231 FloatReg readFloatReg(const StaticInst *si, int idx)
232 {
233 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
234 return thread->readFloatReg(reg_idx);
235 }
236
237 FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
238 {
239 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
240 return thread->readFloatRegBits(reg_idx, width);
241 }
242
243 FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
244 {
245 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
246 return thread->readFloatRegBits(reg_idx);
247 }
248
249 void setIntReg(const StaticInst *si, int idx, uint64_t val)
250 {
251 thread->setIntReg(si->destRegIdx(idx), val);
252 result.integer = val;
253 }
254
255 void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
256 {
257 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
258 thread->setFloatReg(reg_idx, val, width);
259 switch(width) {
260 case 32:
261 result.dbl = (double)val;
262 break;
263 case 64:
264 result.dbl = val;
265 break;
266 };
267 }
268
269 void setFloatReg(const StaticInst *si, int idx, FloatReg val)
270 {
271 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
272 thread->setFloatReg(reg_idx, val);
273 result.dbl = (double)val;
274 }
275
276 void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val,
277 int width)
278 {
279 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
280 thread->setFloatRegBits(reg_idx, val, width);
281 result.integer = val;
282 }
283
284 void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
285 {
286 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
287 thread->setFloatRegBits(reg_idx, val);
288 result.integer = val;
289 }
290
291 uint64_t readPC() { return thread->readPC(); }
292
293 uint64_t readNextPC() { return thread->readNextPC(); }
294
295 void setNextPC(uint64_t val) {
296 thread->setNextPC(val);
297 }
298
299 MiscReg readMiscReg(int misc_reg)
300 {
301 return thread->readMiscReg(misc_reg);
302 }
303
| 148
149#if FULL_SYSTEM
150 Addr dbg_vtophys(Addr addr);
151#endif
152
153 union Result {
154 uint64_t integer;
155// float fp;
156 double dbl;
157 };
158
159 Result result;
160
161 // current instruction
162 MachInst machInst;
163
164 // Pointer to the one memory request.
165 RequestPtr memReq;
166
167 StaticInstPtr curStaticInst;
168
169 // number of simulated instructions
170 Counter numInst;
171 Counter startNumInst;
172
173 std::queue<int> miscRegIdxs;
174
175 virtual Counter totalInstructions() const
176 {
177 return 0;
178 }
179
180 // number of simulated loads
181 Counter numLoad;
182 Counter startNumLoad;
183
184 virtual void serialize(std::ostream &os);
185 virtual void unserialize(Checkpoint *cp, const std::string §ion);
186
187 template <class T>
188 Fault read(Addr addr, T &data, unsigned flags);
189
190 template <class T>
191 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
192
193 // These functions are only used in CPU models that split
194 // effective address computation from the actual memory access.
195 void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); }
196 Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); }
197
198 void prefetch(Addr addr, unsigned flags)
199 {
200 // need to do this...
201 }
202
203 void writeHint(Addr addr, int size, unsigned flags)
204 {
205 // need to do this...
206 }
207
208 Fault copySrcTranslate(Addr src);
209
210 Fault copy(Addr dest);
211
212 // The register accessor methods provide the index of the
213 // instruction's operand (e.g., 0 or 1), not the architectural
214 // register index, to simplify the implementation of register
215 // renaming. We find the architectural register index by indexing
216 // into the instruction's own operand index table. Note that a
217 // raw pointer to the StaticInst is provided instead of a
218 // ref-counted StaticInstPtr to redice overhead. This is fine as
219 // long as these methods don't copy the pointer into any long-term
220 // storage (which is pretty hard to imagine they would have reason
221 // to do).
222
223 uint64_t readIntReg(const StaticInst *si, int idx)
224 {
225 return thread->readIntReg(si->srcRegIdx(idx));
226 }
227
228 FloatReg readFloatReg(const StaticInst *si, int idx, int width)
229 {
230 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
231 return thread->readFloatReg(reg_idx, width);
232 }
233
234 FloatReg readFloatReg(const StaticInst *si, int idx)
235 {
236 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
237 return thread->readFloatReg(reg_idx);
238 }
239
240 FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
241 {
242 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
243 return thread->readFloatRegBits(reg_idx, width);
244 }
245
246 FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
247 {
248 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
249 return thread->readFloatRegBits(reg_idx);
250 }
251
252 void setIntReg(const StaticInst *si, int idx, uint64_t val)
253 {
254 thread->setIntReg(si->destRegIdx(idx), val);
255 result.integer = val;
256 }
257
258 void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
259 {
260 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
261 thread->setFloatReg(reg_idx, val, width);
262 switch(width) {
263 case 32:
264 result.dbl = (double)val;
265 break;
266 case 64:
267 result.dbl = val;
268 break;
269 };
270 }
271
272 void setFloatReg(const StaticInst *si, int idx, FloatReg val)
273 {
274 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
275 thread->setFloatReg(reg_idx, val);
276 result.dbl = (double)val;
277 }
278
279 void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val,
280 int width)
281 {
282 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
283 thread->setFloatRegBits(reg_idx, val, width);
284 result.integer = val;
285 }
286
287 void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
288 {
289 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
290 thread->setFloatRegBits(reg_idx, val);
291 result.integer = val;
292 }
293
294 uint64_t readPC() { return thread->readPC(); }
295
296 uint64_t readNextPC() { return thread->readNextPC(); }
297
298 void setNextPC(uint64_t val) {
299 thread->setNextPC(val);
300 }
301
302 MiscReg readMiscReg(int misc_reg)
303 {
304 return thread->readMiscReg(misc_reg);
305 }
306
|
304 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
| 307 MiscReg readMiscRegWithEffect(int misc_reg)
|
305 {
| 308 {
|
306 return thread->readMiscRegWithEffect(misc_reg, fault);
| 309 return thread->readMiscRegWithEffect(misc_reg);
|
307 }
308
| 310 }
311
|
309 Fault setMiscReg(int misc_reg, const MiscReg &val)
| 312 void setMiscReg(int misc_reg, const MiscReg &val)
|
310 {
311 result.integer = val;
312 miscRegIdxs.push(misc_reg);
313 return thread->setMiscReg(misc_reg, val);
314 }
315
| 313 {
314 result.integer = val;
315 miscRegIdxs.push(misc_reg);
316 return thread->setMiscReg(misc_reg, val);
317 }
318
|
316 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
| 319 void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
|
317 {
318 miscRegIdxs.push(misc_reg);
319 return thread->setMiscRegWithEffect(misc_reg, val);
320 }
321
322 void recordPCChange(uint64_t val) { changedPC = true; newPC = val; }
323 void recordNextPCChange(uint64_t val) { changedNextPC = true; }
324
325 bool translateInstReq(Request *req);
326 void translateDataWriteReq(Request *req);
327 void translateDataReadReq(Request *req);
328
329#if FULL_SYSTEM
330 Fault hwrei() { return thread->hwrei(); }
331 bool inPalMode() { return thread->inPalMode(); }
332 void ev5_trap(Fault fault) { fault->invoke(tc); }
333 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
334#else
335 // Assume that the normal CPU's call to syscall was successful.
336 // The checker's state would have already been updated by the syscall.
337 void syscall(uint64_t callnum) { }
338#endif
339
340 void handleError()
341 {
342 if (exitOnError)
343 dumpAndExit();
344 }
345
346 bool checkFlags(Request *req);
347
348 void dumpAndExit();
349
350 ThreadContext *tcBase() { return tc; }
351 SimpleThread *threadBase() { return thread; }
352
353 Result unverifiedResult;
354 Request *unverifiedReq;
355 uint8_t *unverifiedMemData;
356
357 bool changedPC;
358 bool willChangePC;
359 uint64_t newPC;
360 bool changedNextPC;
361 bool exitOnError;
362 bool updateOnError;
363 bool warnOnlyOnLoadError;
364
365 InstSeqNum youngestSN;
366};
367
368/**
369 * Templated Checker class. This Checker class is templated on the
370 * DynInstPtr of the instruction type that will be verified. Proper
371 * template instantiations of the Checker must be placed at the bottom
372 * of checker/cpu.cc.
373 */
374template <class DynInstPtr>
375class Checker : public CheckerCPU
376{
377 public:
378 Checker(Params *p)
379 : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL)
380 { }
381
382 void switchOut();
383 void takeOverFrom(BaseCPU *oldCPU);
384
385 void verify(DynInstPtr &inst);
386
387 void validateInst(DynInstPtr &inst);
388 void validateExecution(DynInstPtr &inst);
389 void validateState();
390
391 void copyResult(DynInstPtr &inst);
392
393 private:
394 void handleError(DynInstPtr &inst)
395 {
396 if (exitOnError) {
397 dumpAndExit(inst);
398 } else if (updateOnError) {
399 updateThisCycle = true;
400 }
401 }
402
403 void dumpAndExit(DynInstPtr &inst);
404
405 bool updateThisCycle;
406
407 DynInstPtr unverifiedInst;
408
409 std::list<DynInstPtr> instList;
410 typedef typename std::list<DynInstPtr>::iterator InstListIt;
411 void dumpInsts();
412};
413
414#endif // __CPU_CHECKER_CPU_HH__
| 320 {
321 miscRegIdxs.push(misc_reg);
322 return thread->setMiscRegWithEffect(misc_reg, val);
323 }
324
325 void recordPCChange(uint64_t val) { changedPC = true; newPC = val; }
326 void recordNextPCChange(uint64_t val) { changedNextPC = true; }
327
328 bool translateInstReq(Request *req);
329 void translateDataWriteReq(Request *req);
330 void translateDataReadReq(Request *req);
331
332#if FULL_SYSTEM
333 Fault hwrei() { return thread->hwrei(); }
334 bool inPalMode() { return thread->inPalMode(); }
335 void ev5_trap(Fault fault) { fault->invoke(tc); }
336 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
337#else
338 // Assume that the normal CPU's call to syscall was successful.
339 // The checker's state would have already been updated by the syscall.
340 void syscall(uint64_t callnum) { }
341#endif
342
343 void handleError()
344 {
345 if (exitOnError)
346 dumpAndExit();
347 }
348
349 bool checkFlags(Request *req);
350
351 void dumpAndExit();
352
353 ThreadContext *tcBase() { return tc; }
354 SimpleThread *threadBase() { return thread; }
355
356 Result unverifiedResult;
357 Request *unverifiedReq;
358 uint8_t *unverifiedMemData;
359
360 bool changedPC;
361 bool willChangePC;
362 uint64_t newPC;
363 bool changedNextPC;
364 bool exitOnError;
365 bool updateOnError;
366 bool warnOnlyOnLoadError;
367
368 InstSeqNum youngestSN;
369};
370
371/**
372 * Templated Checker class. This Checker class is templated on the
373 * DynInstPtr of the instruction type that will be verified. Proper
374 * template instantiations of the Checker must be placed at the bottom
375 * of checker/cpu.cc.
376 */
377template <class DynInstPtr>
378class Checker : public CheckerCPU
379{
380 public:
381 Checker(Params *p)
382 : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL)
383 { }
384
385 void switchOut();
386 void takeOverFrom(BaseCPU *oldCPU);
387
388 void verify(DynInstPtr &inst);
389
390 void validateInst(DynInstPtr &inst);
391 void validateExecution(DynInstPtr &inst);
392 void validateState();
393
394 void copyResult(DynInstPtr &inst);
395
396 private:
397 void handleError(DynInstPtr &inst)
398 {
399 if (exitOnError) {
400 dumpAndExit(inst);
401 } else if (updateOnError) {
402 updateThisCycle = true;
403 }
404 }
405
406 void dumpAndExit(DynInstPtr &inst);
407
408 bool updateThisCycle;
409
410 DynInstPtr unverifiedInst;
411
412 std::list<DynInstPtr> instList;
413 typedef typename std::list<DynInstPtr>::iterator InstListIt;
414 void dumpInsts();
415};
416
417#endif // __CPU_CHECKER_CPU_HH__
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