1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_CHECKER_CPU_HH__
32#define __CPU_CHECKER_CPU_HH__
33
34#include <list>
35#include <queue>
36#include <map>
37
38#include "arch/types.hh"
39#include "base/statistics.hh"
40#include "config/full_system.hh"
41#include "cpu/base.hh"
42#include "cpu/base_dyn_inst.hh"
43#include "cpu/simple_thread.hh"
44#include "cpu/pc_event.hh"
45#include "cpu/static_inst.hh"
46#include "sim/eventq.hh"
47
48// forward declarations
49#if FULL_SYSTEM
50class Processor;
51class AlphaITB;
52class AlphaDTB;
53class PhysicalMemory;
54
55class RemoteGDB;
56class GDBListener;
57
58#else
59
60class Process;
61
62#endif // FULL_SYSTEM
63template <class>
64class BaseDynInst;
65class ThreadContext;
66class MemInterface;
67class Checkpoint;
68class Request;
69
70/**
71 * CheckerCPU class. Dynamically verifies instructions as they are
72 * completed by making sure that the instruction and its results match
73 * the independent execution of the benchmark inside the checker. The
74 * checker verifies instructions in order, regardless of the order in
75 * which instructions complete. There are certain results that can
76 * not be verified, specifically the result of a store conditional or
77 * the values of uncached accesses. In these cases, and with
78 * instructions marked as "IsUnverifiable", the checker assumes that
79 * the value from the main CPU's execution is correct and simply
80 * copies that value. It provides a CheckerThreadContext (see
81 * checker/thread_context.hh) that provides hooks for updating the
82 * Checker's state through any ThreadContext accesses. This allows the
83 * checker to be able to correctly verify instructions, even with
84 * external accesses to the ThreadContext that change state.
85 */
86class CheckerCPU : public BaseCPU
87{
88 protected:
89 typedef TheISA::MachInst MachInst;
90 typedef TheISA::FloatReg FloatReg;
91 typedef TheISA::FloatRegBits FloatRegBits;
92 typedef TheISA::MiscReg MiscReg;
93 public:
94 virtual void init();
95
96 struct Params : public BaseCPU::Params
97 {
98#if FULL_SYSTEM
99 AlphaITB *itb;
100 AlphaDTB *dtb;
101#else
102 Process *process;
103#endif
104 bool exitOnError;
105 bool warnOnlyOnLoadError;
106 };
107
108 public:
109 CheckerCPU(Params *p);
110 virtual ~CheckerCPU();
111
112 Process *process;
113
114 void setMemory(MemObject *mem);
115
116 MemObject *memPtr;
117
118 void setSystem(System *system);
119
120 System *systemPtr;
121
122 void setIcachePort(Port *icache_port);
123
124 Port *icachePort;
125
126 void setDcachePort(Port *dcache_port);
127
128 Port *dcachePort;
129
130 virtual Port *getPort(const std::string &name, int idx)
131 {
132 panic("Not supported on checker!");
133 return NULL;
134 }
135
136 public:
137 // Primary thread being run.
138 SimpleThread *thread;
139
140 ThreadContext *tc;
141
142 AlphaITB *itb;
143 AlphaDTB *dtb;
144
145#if FULL_SYSTEM
146 Addr dbg_vtophys(Addr addr);
147#endif
148
149 union Result {
150 uint64_t integer;
151 float fp;
152 double dbl;
153 };
154
155 Result result;
156
157 // current instruction
158 MachInst machInst;
159
160 // Pointer to the one memory request.
161 RequestPtr memReq;
162
163 StaticInstPtr curStaticInst;
164
165 // number of simulated instructions
166 Counter numInst;
167 Counter startNumInst;
168
169 std::queue<int> miscRegIdxs;
170
171 virtual Counter totalInstructions() const
172 {
| 1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_CHECKER_CPU_HH__
32#define __CPU_CHECKER_CPU_HH__
33
34#include <list>
35#include <queue>
36#include <map>
37
38#include "arch/types.hh"
39#include "base/statistics.hh"
40#include "config/full_system.hh"
41#include "cpu/base.hh"
42#include "cpu/base_dyn_inst.hh"
43#include "cpu/simple_thread.hh"
44#include "cpu/pc_event.hh"
45#include "cpu/static_inst.hh"
46#include "sim/eventq.hh"
47
48// forward declarations
49#if FULL_SYSTEM
50class Processor;
51class AlphaITB;
52class AlphaDTB;
53class PhysicalMemory;
54
55class RemoteGDB;
56class GDBListener;
57
58#else
59
60class Process;
61
62#endif // FULL_SYSTEM
63template <class>
64class BaseDynInst;
65class ThreadContext;
66class MemInterface;
67class Checkpoint;
68class Request;
69
70/**
71 * CheckerCPU class. Dynamically verifies instructions as they are
72 * completed by making sure that the instruction and its results match
73 * the independent execution of the benchmark inside the checker. The
74 * checker verifies instructions in order, regardless of the order in
75 * which instructions complete. There are certain results that can
76 * not be verified, specifically the result of a store conditional or
77 * the values of uncached accesses. In these cases, and with
78 * instructions marked as "IsUnverifiable", the checker assumes that
79 * the value from the main CPU's execution is correct and simply
80 * copies that value. It provides a CheckerThreadContext (see
81 * checker/thread_context.hh) that provides hooks for updating the
82 * Checker's state through any ThreadContext accesses. This allows the
83 * checker to be able to correctly verify instructions, even with
84 * external accesses to the ThreadContext that change state.
85 */
86class CheckerCPU : public BaseCPU
87{
88 protected:
89 typedef TheISA::MachInst MachInst;
90 typedef TheISA::FloatReg FloatReg;
91 typedef TheISA::FloatRegBits FloatRegBits;
92 typedef TheISA::MiscReg MiscReg;
93 public:
94 virtual void init();
95
96 struct Params : public BaseCPU::Params
97 {
98#if FULL_SYSTEM
99 AlphaITB *itb;
100 AlphaDTB *dtb;
101#else
102 Process *process;
103#endif
104 bool exitOnError;
105 bool warnOnlyOnLoadError;
106 };
107
108 public:
109 CheckerCPU(Params *p);
110 virtual ~CheckerCPU();
111
112 Process *process;
113
114 void setMemory(MemObject *mem);
115
116 MemObject *memPtr;
117
118 void setSystem(System *system);
119
120 System *systemPtr;
121
122 void setIcachePort(Port *icache_port);
123
124 Port *icachePort;
125
126 void setDcachePort(Port *dcache_port);
127
128 Port *dcachePort;
129
130 virtual Port *getPort(const std::string &name, int idx)
131 {
132 panic("Not supported on checker!");
133 return NULL;
134 }
135
136 public:
137 // Primary thread being run.
138 SimpleThread *thread;
139
140 ThreadContext *tc;
141
142 AlphaITB *itb;
143 AlphaDTB *dtb;
144
145#if FULL_SYSTEM
146 Addr dbg_vtophys(Addr addr);
147#endif
148
149 union Result {
150 uint64_t integer;
151 float fp;
152 double dbl;
153 };
154
155 Result result;
156
157 // current instruction
158 MachInst machInst;
159
160 // Pointer to the one memory request.
161 RequestPtr memReq;
162
163 StaticInstPtr curStaticInst;
164
165 // number of simulated instructions
166 Counter numInst;
167 Counter startNumInst;
168
169 std::queue<int> miscRegIdxs;
170
171 virtual Counter totalInstructions() const
172 {
|
174 }
175
176 // number of simulated loads
177 Counter numLoad;
178 Counter startNumLoad;
179
180 virtual void serialize(std::ostream &os);
181 virtual void unserialize(Checkpoint *cp, const std::string §ion);
182
183 template <class T>
184 Fault read(Addr addr, T &data, unsigned flags);
185
186 template <class T>
187 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
188
189 // These functions are only used in CPU models that split
190 // effective address computation from the actual memory access.
191 void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); }
192 Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); }
193
194 void prefetch(Addr addr, unsigned flags)
195 {
196 // need to do this...
197 }
198
199 void writeHint(Addr addr, int size, unsigned flags)
200 {
201 // need to do this...
202 }
203
204 Fault copySrcTranslate(Addr src);
205
206 Fault copy(Addr dest);
207
208 // The register accessor methods provide the index of the
209 // instruction's operand (e.g., 0 or 1), not the architectural
210 // register index, to simplify the implementation of register
211 // renaming. We find the architectural register index by indexing
212 // into the instruction's own operand index table. Note that a
213 // raw pointer to the StaticInst is provided instead of a
214 // ref-counted StaticInstPtr to redice overhead. This is fine as
215 // long as these methods don't copy the pointer into any long-term
216 // storage (which is pretty hard to imagine they would have reason
217 // to do).
218
219 uint64_t readIntReg(const StaticInst *si, int idx)
220 {
221 return thread->readIntReg(si->srcRegIdx(idx));
222 }
223
224 FloatReg readFloatReg(const StaticInst *si, int idx, int width)
225 {
226 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
227 return thread->readFloatReg(reg_idx, width);
228 }
229
230 FloatReg readFloatReg(const StaticInst *si, int idx)
231 {
232 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
233 return thread->readFloatReg(reg_idx);
234 }
235
236 FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
237 {
238 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
239 return thread->readFloatRegBits(reg_idx, width);
240 }
241
242 FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
243 {
244 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
245 return thread->readFloatRegBits(reg_idx);
246 }
247
248 void setIntReg(const StaticInst *si, int idx, uint64_t val)
249 {
250 thread->setIntReg(si->destRegIdx(idx), val);
251 result.integer = val;
252 }
253
254 void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
255 {
256 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
257 thread->setFloatReg(reg_idx, val, width);
258 switch(width) {
259 case 32:
260 result.fp = val;
261 break;
262 case 64:
263 result.dbl = val;
264 break;
265 };
266 }
267
268 void setFloatReg(const StaticInst *si, int idx, FloatReg val)
269 {
270 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
271 thread->setFloatReg(reg_idx, val);
272 result.fp = val;
273 }
274
275 void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val,
276 int width)
277 {
278 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
279 thread->setFloatRegBits(reg_idx, val, width);
280 result.integer = val;
281 }
282
283 void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
284 {
285 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
286 thread->setFloatRegBits(reg_idx, val);
287 result.integer = val;
288 }
289
290 uint64_t readPC() { return thread->readPC(); }
291
292 uint64_t readNextPC() { return thread->readNextPC(); }
293
294 void setNextPC(uint64_t val) {
295 thread->setNextPC(val);
296 }
297
298 MiscReg readMiscReg(int misc_reg)
299 {
300 return thread->readMiscReg(misc_reg);
301 }
302
303 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
304 {
305 return thread->readMiscRegWithEffect(misc_reg, fault);
306 }
307
308 Fault setMiscReg(int misc_reg, const MiscReg &val)
309 {
310 result.integer = val;
311 miscRegIdxs.push(misc_reg);
312 return thread->setMiscReg(misc_reg, val);
313 }
314
315 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
316 {
317 miscRegIdxs.push(misc_reg);
318 return thread->setMiscRegWithEffect(misc_reg, val);
319 }
320
321 void recordPCChange(uint64_t val) { changedPC = true; }
322 void recordNextPCChange(uint64_t val) { changedNextPC = true; }
323
324 bool translateInstReq(Request *req);
325 void translateDataWriteReq(Request *req);
326 void translateDataReadReq(Request *req);
327
328#if FULL_SYSTEM
329 Fault hwrei() { return thread->hwrei(); }
330 int readIntrFlag() { return thread->readIntrFlag(); }
331 void setIntrFlag(int val) { thread->setIntrFlag(val); }
332 bool inPalMode() { return thread->inPalMode(); }
333 void ev5_trap(Fault fault) { fault->invoke(tc); }
334 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
335#else
336 // Assume that the normal CPU's call to syscall was successful.
337 // The checker's state would have already been updated by the syscall.
338 void syscall(uint64_t callnum) { }
339#endif
340
341 void handleError()
342 {
343 if (exitOnError)
344 dumpAndExit();
345 }
346
347 bool checkFlags(Request *req);
348
349 void dumpAndExit();
350
351 ThreadContext *tcBase() { return tc; }
352 SimpleThread *threadBase() { return thread; }
353
354 Result unverifiedResult;
355 Request *unverifiedReq;
356 uint8_t *unverifiedMemData;
357
358 bool changedPC;
359 bool willChangePC;
360 uint64_t newPC;
361 bool changedNextPC;
362 bool exitOnError;
363 bool warnOnlyOnLoadError;
364
365 InstSeqNum youngestSN;
366};
367
368/**
369 * Templated Checker class. This Checker class is templated on the
370 * DynInstPtr of the instruction type that will be verified. Proper
371 * template instantiations of the Checker must be placed at the bottom
372 * of checker/cpu.cc.
373 */
374template <class DynInstPtr>
375class Checker : public CheckerCPU
376{
377 public:
378 Checker(Params *p)
379 : CheckerCPU(p)
380 { }
381
382 void switchOut();
383 void takeOverFrom(BaseCPU *oldCPU);
384
385 void verify(DynInstPtr &inst);
386
387 void validateInst(DynInstPtr &inst);
388 void validateExecution(DynInstPtr &inst);
389 void validateState();
390
391 void copyResult(DynInstPtr &inst);
392
393 private:
394 void handleError(DynInstPtr &inst)
395 {
396 if (exitOnError)
397 dumpAndExit(inst);
398 }
399
400 void dumpAndExit(DynInstPtr &inst);
401
402 std::list<DynInstPtr> instList;
403 typedef typename std::list<DynInstPtr>::iterator InstListIt;
404 void dumpInsts();
405};
406
407#endif // __CPU_CHECKER_CPU_HH__
| 174 }
175
176 // number of simulated loads
177 Counter numLoad;
178 Counter startNumLoad;
179
180 virtual void serialize(std::ostream &os);
181 virtual void unserialize(Checkpoint *cp, const std::string §ion);
182
183 template <class T>
184 Fault read(Addr addr, T &data, unsigned flags);
185
186 template <class T>
187 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
188
189 // These functions are only used in CPU models that split
190 // effective address computation from the actual memory access.
191 void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); }
192 Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); }
193
194 void prefetch(Addr addr, unsigned flags)
195 {
196 // need to do this...
197 }
198
199 void writeHint(Addr addr, int size, unsigned flags)
200 {
201 // need to do this...
202 }
203
204 Fault copySrcTranslate(Addr src);
205
206 Fault copy(Addr dest);
207
208 // The register accessor methods provide the index of the
209 // instruction's operand (e.g., 0 or 1), not the architectural
210 // register index, to simplify the implementation of register
211 // renaming. We find the architectural register index by indexing
212 // into the instruction's own operand index table. Note that a
213 // raw pointer to the StaticInst is provided instead of a
214 // ref-counted StaticInstPtr to redice overhead. This is fine as
215 // long as these methods don't copy the pointer into any long-term
216 // storage (which is pretty hard to imagine they would have reason
217 // to do).
218
219 uint64_t readIntReg(const StaticInst *si, int idx)
220 {
221 return thread->readIntReg(si->srcRegIdx(idx));
222 }
223
224 FloatReg readFloatReg(const StaticInst *si, int idx, int width)
225 {
226 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
227 return thread->readFloatReg(reg_idx, width);
228 }
229
230 FloatReg readFloatReg(const StaticInst *si, int idx)
231 {
232 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
233 return thread->readFloatReg(reg_idx);
234 }
235
236 FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
237 {
238 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
239 return thread->readFloatRegBits(reg_idx, width);
240 }
241
242 FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
243 {
244 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
245 return thread->readFloatRegBits(reg_idx);
246 }
247
248 void setIntReg(const StaticInst *si, int idx, uint64_t val)
249 {
250 thread->setIntReg(si->destRegIdx(idx), val);
251 result.integer = val;
252 }
253
254 void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
255 {
256 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
257 thread->setFloatReg(reg_idx, val, width);
258 switch(width) {
259 case 32:
260 result.fp = val;
261 break;
262 case 64:
263 result.dbl = val;
264 break;
265 };
266 }
267
268 void setFloatReg(const StaticInst *si, int idx, FloatReg val)
269 {
270 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
271 thread->setFloatReg(reg_idx, val);
272 result.fp = val;
273 }
274
275 void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val,
276 int width)
277 {
278 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
279 thread->setFloatRegBits(reg_idx, val, width);
280 result.integer = val;
281 }
282
283 void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
284 {
285 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
286 thread->setFloatRegBits(reg_idx, val);
287 result.integer = val;
288 }
289
290 uint64_t readPC() { return thread->readPC(); }
291
292 uint64_t readNextPC() { return thread->readNextPC(); }
293
294 void setNextPC(uint64_t val) {
295 thread->setNextPC(val);
296 }
297
298 MiscReg readMiscReg(int misc_reg)
299 {
300 return thread->readMiscReg(misc_reg);
301 }
302
303 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
304 {
305 return thread->readMiscRegWithEffect(misc_reg, fault);
306 }
307
308 Fault setMiscReg(int misc_reg, const MiscReg &val)
309 {
310 result.integer = val;
311 miscRegIdxs.push(misc_reg);
312 return thread->setMiscReg(misc_reg, val);
313 }
314
315 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
316 {
317 miscRegIdxs.push(misc_reg);
318 return thread->setMiscRegWithEffect(misc_reg, val);
319 }
320
321 void recordPCChange(uint64_t val) { changedPC = true; }
322 void recordNextPCChange(uint64_t val) { changedNextPC = true; }
323
324 bool translateInstReq(Request *req);
325 void translateDataWriteReq(Request *req);
326 void translateDataReadReq(Request *req);
327
328#if FULL_SYSTEM
329 Fault hwrei() { return thread->hwrei(); }
330 int readIntrFlag() { return thread->readIntrFlag(); }
331 void setIntrFlag(int val) { thread->setIntrFlag(val); }
332 bool inPalMode() { return thread->inPalMode(); }
333 void ev5_trap(Fault fault) { fault->invoke(tc); }
334 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
335#else
336 // Assume that the normal CPU's call to syscall was successful.
337 // The checker's state would have already been updated by the syscall.
338 void syscall(uint64_t callnum) { }
339#endif
340
341 void handleError()
342 {
343 if (exitOnError)
344 dumpAndExit();
345 }
346
347 bool checkFlags(Request *req);
348
349 void dumpAndExit();
350
351 ThreadContext *tcBase() { return tc; }
352 SimpleThread *threadBase() { return thread; }
353
354 Result unverifiedResult;
355 Request *unverifiedReq;
356 uint8_t *unverifiedMemData;
357
358 bool changedPC;
359 bool willChangePC;
360 uint64_t newPC;
361 bool changedNextPC;
362 bool exitOnError;
363 bool warnOnlyOnLoadError;
364
365 InstSeqNum youngestSN;
366};
367
368/**
369 * Templated Checker class. This Checker class is templated on the
370 * DynInstPtr of the instruction type that will be verified. Proper
371 * template instantiations of the Checker must be placed at the bottom
372 * of checker/cpu.cc.
373 */
374template <class DynInstPtr>
375class Checker : public CheckerCPU
376{
377 public:
378 Checker(Params *p)
379 : CheckerCPU(p)
380 { }
381
382 void switchOut();
383 void takeOverFrom(BaseCPU *oldCPU);
384
385 void verify(DynInstPtr &inst);
386
387 void validateInst(DynInstPtr &inst);
388 void validateExecution(DynInstPtr &inst);
389 void validateState();
390
391 void copyResult(DynInstPtr &inst);
392
393 private:
394 void handleError(DynInstPtr &inst)
395 {
396 if (exitOnError)
397 dumpAndExit(inst);
398 }
399
400 void dumpAndExit(DynInstPtr &inst);
401
402 std::list<DynInstPtr> instList;
403 typedef typename std::list<DynInstPtr>::iterator InstListIt;
404 void dumpInsts();
405};
406
407#endif // __CPU_CHECKER_CPU_HH__
|