1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_CHECKER_CPU_HH__
32#define __CPU_CHECKER_CPU_HH__
33
34#include <list>
35#include <queue>
36#include <map>
37
38#include "arch/types.hh"
39#include "base/statistics.hh"
40#include "config/full_system.hh"
41#include "cpu/base.hh"
42#include "cpu/base_dyn_inst.hh"
43#include "cpu/simple_thread.hh"
44#include "cpu/pc_event.hh"
45#include "cpu/static_inst.hh"
46#include "sim/eventq.hh"
47
48// forward declarations
49#if FULL_SYSTEM
50class Processor;
51class AlphaITB;
52class AlphaDTB;
53class PhysicalMemory;
54
55class RemoteGDB;
56class GDBListener;
57
58#else
59
60class Process;
61
62#endif // FULL_SYSTEM
63template <class>
64class BaseDynInst;
65class ThreadContext;
66class MemInterface;
67class Checkpoint;
68class Request;
69class Sampler;
70
71/**
72 * CheckerCPU class. Dynamically verifies instructions as they are
73 * completed by making sure that the instruction and its results match
74 * the independent execution of the benchmark inside the checker. The
75 * checker verifies instructions in order, regardless of the order in
76 * which instructions complete. There are certain results that can
77 * not be verified, specifically the result of a store conditional or
78 * the values of uncached accesses. In these cases, and with
79 * instructions marked as "IsUnverifiable", the checker assumes that
80 * the value from the main CPU's execution is correct and simply
81 * copies that value. It provides a CheckerThreadContext (see
82 * checker/thread_context.hh) that provides hooks for updating the
83 * Checker's state through any ThreadContext accesses. This allows the
84 * checker to be able to correctly verify instructions, even with
85 * external accesses to the ThreadContext that change state.
86 */
87class CheckerCPU : public BaseCPU
88{
89 protected:
90 typedef TheISA::MachInst MachInst;
91 typedef TheISA::FloatReg FloatReg;
92 typedef TheISA::FloatRegBits FloatRegBits;
93 typedef TheISA::MiscReg MiscReg;
94 public:
95 virtual void init();
96
97 struct Params : public BaseCPU::Params
98 {
99#if FULL_SYSTEM
100 AlphaITB *itb;
101 AlphaDTB *dtb;
| 1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_CHECKER_CPU_HH__
32#define __CPU_CHECKER_CPU_HH__
33
34#include <list>
35#include <queue>
36#include <map>
37
38#include "arch/types.hh"
39#include "base/statistics.hh"
40#include "config/full_system.hh"
41#include "cpu/base.hh"
42#include "cpu/base_dyn_inst.hh"
43#include "cpu/simple_thread.hh"
44#include "cpu/pc_event.hh"
45#include "cpu/static_inst.hh"
46#include "sim/eventq.hh"
47
48// forward declarations
49#if FULL_SYSTEM
50class Processor;
51class AlphaITB;
52class AlphaDTB;
53class PhysicalMemory;
54
55class RemoteGDB;
56class GDBListener;
57
58#else
59
60class Process;
61
62#endif // FULL_SYSTEM
63template <class>
64class BaseDynInst;
65class ThreadContext;
66class MemInterface;
67class Checkpoint;
68class Request;
69class Sampler;
70
71/**
72 * CheckerCPU class. Dynamically verifies instructions as they are
73 * completed by making sure that the instruction and its results match
74 * the independent execution of the benchmark inside the checker. The
75 * checker verifies instructions in order, regardless of the order in
76 * which instructions complete. There are certain results that can
77 * not be verified, specifically the result of a store conditional or
78 * the values of uncached accesses. In these cases, and with
79 * instructions marked as "IsUnverifiable", the checker assumes that
80 * the value from the main CPU's execution is correct and simply
81 * copies that value. It provides a CheckerThreadContext (see
82 * checker/thread_context.hh) that provides hooks for updating the
83 * Checker's state through any ThreadContext accesses. This allows the
84 * checker to be able to correctly verify instructions, even with
85 * external accesses to the ThreadContext that change state.
86 */
87class CheckerCPU : public BaseCPU
88{
89 protected:
90 typedef TheISA::MachInst MachInst;
91 typedef TheISA::FloatReg FloatReg;
92 typedef TheISA::FloatRegBits FloatRegBits;
93 typedef TheISA::MiscReg MiscReg;
94 public:
95 virtual void init();
96
97 struct Params : public BaseCPU::Params
98 {
99#if FULL_SYSTEM
100 AlphaITB *itb;
101 AlphaDTB *dtb;
|
124
125 void setIcachePort(Port *icache_port);
126
127 Port *icachePort;
128
129 void setDcachePort(Port *dcache_port);
130
131 Port *dcachePort;
132
133 public:
134 // Primary thread being run.
135 SimpleThread *thread;
136
137 ThreadContext *tc;
138
139 AlphaITB *itb;
140 AlphaDTB *dtb;
141
142#if FULL_SYSTEM
143 Addr dbg_vtophys(Addr addr);
144#endif
145
146 union Result {
147 uint64_t integer;
148 float fp;
149 double dbl;
150 };
151
152 Result result;
153
154 // current instruction
155 MachInst machInst;
156
157 // Pointer to the one memory request.
158 RequestPtr memReq;
159
160 StaticInstPtr curStaticInst;
161
162 // number of simulated instructions
163 Counter numInst;
164 Counter startNumInst;
165
166 std::queue<int> miscRegIdxs;
167
168 virtual Counter totalInstructions() const
169 {
170 return numInst - startNumInst;
171 }
172
173 // number of simulated loads
174 Counter numLoad;
175 Counter startNumLoad;
176
177 virtual void serialize(std::ostream &os);
178 virtual void unserialize(Checkpoint *cp, const std::string §ion);
179
180 template <class T>
181 Fault read(Addr addr, T &data, unsigned flags);
182
183 template <class T>
184 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
185
186 // These functions are only used in CPU models that split
187 // effective address computation from the actual memory access.
188 void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); }
189 Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); }
190
191 void prefetch(Addr addr, unsigned flags)
192 {
193 // need to do this...
194 }
195
196 void writeHint(Addr addr, int size, unsigned flags)
197 {
198 // need to do this...
199 }
200
201 Fault copySrcTranslate(Addr src);
202
203 Fault copy(Addr dest);
204
205 // The register accessor methods provide the index of the
206 // instruction's operand (e.g., 0 or 1), not the architectural
207 // register index, to simplify the implementation of register
208 // renaming. We find the architectural register index by indexing
209 // into the instruction's own operand index table. Note that a
210 // raw pointer to the StaticInst is provided instead of a
211 // ref-counted StaticInstPtr to redice overhead. This is fine as
212 // long as these methods don't copy the pointer into any long-term
213 // storage (which is pretty hard to imagine they would have reason
214 // to do).
215
216 uint64_t readIntReg(const StaticInst *si, int idx)
217 {
218 return thread->readIntReg(si->srcRegIdx(idx));
219 }
220
221 FloatReg readFloatReg(const StaticInst *si, int idx, int width)
222 {
223 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
224 return thread->readFloatReg(reg_idx, width);
225 }
226
227 FloatReg readFloatReg(const StaticInst *si, int idx)
228 {
229 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
230 return thread->readFloatReg(reg_idx);
231 }
232
233 FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
234 {
235 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
236 return thread->readFloatRegBits(reg_idx, width);
237 }
238
239 FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
240 {
241 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
242 return thread->readFloatRegBits(reg_idx);
243 }
244
245 void setIntReg(const StaticInst *si, int idx, uint64_t val)
246 {
247 thread->setIntReg(si->destRegIdx(idx), val);
248 result.integer = val;
249 }
250
251 void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
252 {
253 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
254 thread->setFloatReg(reg_idx, val, width);
255 switch(width) {
256 case 32:
257 result.fp = val;
258 break;
259 case 64:
260 result.dbl = val;
261 break;
262 };
263 }
264
265 void setFloatReg(const StaticInst *si, int idx, FloatReg val)
266 {
267 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
268 thread->setFloatReg(reg_idx, val);
269 result.fp = val;
270 }
271
272 void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val,
273 int width)
274 {
275 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
276 thread->setFloatRegBits(reg_idx, val, width);
277 result.integer = val;
278 }
279
280 void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
281 {
282 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
283 thread->setFloatRegBits(reg_idx, val);
284 result.integer = val;
285 }
286
287 uint64_t readPC() { return thread->readPC(); }
288
289 uint64_t readNextPC() { return thread->readNextPC(); }
290
291 void setNextPC(uint64_t val) {
292 thread->setNextPC(val);
293 }
294
295 MiscReg readMiscReg(int misc_reg)
296 {
297 return thread->readMiscReg(misc_reg);
298 }
299
300 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
301 {
302 return thread->readMiscRegWithEffect(misc_reg, fault);
303 }
304
305 Fault setMiscReg(int misc_reg, const MiscReg &val)
306 {
307 result.integer = val;
308 miscRegIdxs.push(misc_reg);
309 return thread->setMiscReg(misc_reg, val);
310 }
311
312 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
313 {
314 miscRegIdxs.push(misc_reg);
315 return thread->setMiscRegWithEffect(misc_reg, val);
316 }
317
318 void recordPCChange(uint64_t val) { changedPC = true; }
319 void recordNextPCChange(uint64_t val) { changedNextPC = true; }
320
321 bool translateInstReq(Request *req);
322 void translateDataWriteReq(Request *req);
323 void translateDataReadReq(Request *req);
324
325#if FULL_SYSTEM
326 Fault hwrei() { return thread->hwrei(); }
327 int readIntrFlag() { return thread->readIntrFlag(); }
328 void setIntrFlag(int val) { thread->setIntrFlag(val); }
329 bool inPalMode() { return thread->inPalMode(); }
| 121
122 void setIcachePort(Port *icache_port);
123
124 Port *icachePort;
125
126 void setDcachePort(Port *dcache_port);
127
128 Port *dcachePort;
129
130 public:
131 // Primary thread being run.
132 SimpleThread *thread;
133
134 ThreadContext *tc;
135
136 AlphaITB *itb;
137 AlphaDTB *dtb;
138
139#if FULL_SYSTEM
140 Addr dbg_vtophys(Addr addr);
141#endif
142
143 union Result {
144 uint64_t integer;
145 float fp;
146 double dbl;
147 };
148
149 Result result;
150
151 // current instruction
152 MachInst machInst;
153
154 // Pointer to the one memory request.
155 RequestPtr memReq;
156
157 StaticInstPtr curStaticInst;
158
159 // number of simulated instructions
160 Counter numInst;
161 Counter startNumInst;
162
163 std::queue<int> miscRegIdxs;
164
165 virtual Counter totalInstructions() const
166 {
167 return numInst - startNumInst;
168 }
169
170 // number of simulated loads
171 Counter numLoad;
172 Counter startNumLoad;
173
174 virtual void serialize(std::ostream &os);
175 virtual void unserialize(Checkpoint *cp, const std::string §ion);
176
177 template <class T>
178 Fault read(Addr addr, T &data, unsigned flags);
179
180 template <class T>
181 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
182
183 // These functions are only used in CPU models that split
184 // effective address computation from the actual memory access.
185 void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); }
186 Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); }
187
188 void prefetch(Addr addr, unsigned flags)
189 {
190 // need to do this...
191 }
192
193 void writeHint(Addr addr, int size, unsigned flags)
194 {
195 // need to do this...
196 }
197
198 Fault copySrcTranslate(Addr src);
199
200 Fault copy(Addr dest);
201
202 // The register accessor methods provide the index of the
203 // instruction's operand (e.g., 0 or 1), not the architectural
204 // register index, to simplify the implementation of register
205 // renaming. We find the architectural register index by indexing
206 // into the instruction's own operand index table. Note that a
207 // raw pointer to the StaticInst is provided instead of a
208 // ref-counted StaticInstPtr to redice overhead. This is fine as
209 // long as these methods don't copy the pointer into any long-term
210 // storage (which is pretty hard to imagine they would have reason
211 // to do).
212
213 uint64_t readIntReg(const StaticInst *si, int idx)
214 {
215 return thread->readIntReg(si->srcRegIdx(idx));
216 }
217
218 FloatReg readFloatReg(const StaticInst *si, int idx, int width)
219 {
220 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
221 return thread->readFloatReg(reg_idx, width);
222 }
223
224 FloatReg readFloatReg(const StaticInst *si, int idx)
225 {
226 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
227 return thread->readFloatReg(reg_idx);
228 }
229
230 FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
231 {
232 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
233 return thread->readFloatRegBits(reg_idx, width);
234 }
235
236 FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
237 {
238 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
239 return thread->readFloatRegBits(reg_idx);
240 }
241
242 void setIntReg(const StaticInst *si, int idx, uint64_t val)
243 {
244 thread->setIntReg(si->destRegIdx(idx), val);
245 result.integer = val;
246 }
247
248 void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
249 {
250 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
251 thread->setFloatReg(reg_idx, val, width);
252 switch(width) {
253 case 32:
254 result.fp = val;
255 break;
256 case 64:
257 result.dbl = val;
258 break;
259 };
260 }
261
262 void setFloatReg(const StaticInst *si, int idx, FloatReg val)
263 {
264 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
265 thread->setFloatReg(reg_idx, val);
266 result.fp = val;
267 }
268
269 void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val,
270 int width)
271 {
272 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
273 thread->setFloatRegBits(reg_idx, val, width);
274 result.integer = val;
275 }
276
277 void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
278 {
279 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
280 thread->setFloatRegBits(reg_idx, val);
281 result.integer = val;
282 }
283
284 uint64_t readPC() { return thread->readPC(); }
285
286 uint64_t readNextPC() { return thread->readNextPC(); }
287
288 void setNextPC(uint64_t val) {
289 thread->setNextPC(val);
290 }
291
292 MiscReg readMiscReg(int misc_reg)
293 {
294 return thread->readMiscReg(misc_reg);
295 }
296
297 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
298 {
299 return thread->readMiscRegWithEffect(misc_reg, fault);
300 }
301
302 Fault setMiscReg(int misc_reg, const MiscReg &val)
303 {
304 result.integer = val;
305 miscRegIdxs.push(misc_reg);
306 return thread->setMiscReg(misc_reg, val);
307 }
308
309 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
310 {
311 miscRegIdxs.push(misc_reg);
312 return thread->setMiscRegWithEffect(misc_reg, val);
313 }
314
315 void recordPCChange(uint64_t val) { changedPC = true; }
316 void recordNextPCChange(uint64_t val) { changedNextPC = true; }
317
318 bool translateInstReq(Request *req);
319 void translateDataWriteReq(Request *req);
320 void translateDataReadReq(Request *req);
321
322#if FULL_SYSTEM
323 Fault hwrei() { return thread->hwrei(); }
324 int readIntrFlag() { return thread->readIntrFlag(); }
325 void setIntrFlag(int val) { thread->setIntrFlag(val); }
326 bool inPalMode() { return thread->inPalMode(); }
|