1/*
2 * Copyright (c) 2011 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_CHECKER_CPU_HH__
45#define __CPU_CHECKER_CPU_HH__
46
47#include <list>
48#include <map>
49#include <queue>
50
51#include "arch/types.hh"
52#include "base/statistics.hh"
53#include "cpu/base.hh"
54#include "cpu/base_dyn_inst.hh"
55#include "cpu/exec_context.hh"
56#include "cpu/pc_event.hh"
57#include "cpu/simple_thread.hh"
58#include "cpu/static_inst.hh"
59#include "debug/Checker.hh"
60#include "params/CheckerCPU.hh"
61#include "sim/eventq.hh"
62
63// forward declarations
64namespace TheISA
65{
66 class TLB;
67}
68
69template <class>
70class BaseDynInst;
71class ThreadContext;
72class Request;
73
74/**
75 * CheckerCPU class. Dynamically verifies instructions as they are
76 * completed by making sure that the instruction and its results match
77 * the independent execution of the benchmark inside the checker. The
78 * checker verifies instructions in order, regardless of the order in
79 * which instructions complete. There are certain results that can
80 * not be verified, specifically the result of a store conditional or
81 * the values of uncached accesses. In these cases, and with
82 * instructions marked as "IsUnverifiable", the checker assumes that
83 * the value from the main CPU's execution is correct and simply
84 * copies that value. It provides a CheckerThreadContext (see
85 * checker/thread_context.hh) that provides hooks for updating the
86 * Checker's state through any ThreadContext accesses. This allows the
87 * checker to be able to correctly verify instructions, even with
88 * external accesses to the ThreadContext that change state.
89 */
90class CheckerCPU : public BaseCPU, public ExecContext
91{
92 protected:
93 typedef TheISA::MachInst MachInst;
94 typedef TheISA::FloatReg FloatReg;
95 typedef TheISA::FloatRegBits FloatRegBits;
96 typedef TheISA::MiscReg MiscReg;
| 1/*
2 * Copyright (c) 2011 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 */
43
44#ifndef __CPU_CHECKER_CPU_HH__
45#define __CPU_CHECKER_CPU_HH__
46
47#include <list>
48#include <map>
49#include <queue>
50
51#include "arch/types.hh"
52#include "base/statistics.hh"
53#include "cpu/base.hh"
54#include "cpu/base_dyn_inst.hh"
55#include "cpu/exec_context.hh"
56#include "cpu/pc_event.hh"
57#include "cpu/simple_thread.hh"
58#include "cpu/static_inst.hh"
59#include "debug/Checker.hh"
60#include "params/CheckerCPU.hh"
61#include "sim/eventq.hh"
62
63// forward declarations
64namespace TheISA
65{
66 class TLB;
67}
68
69template <class>
70class BaseDynInst;
71class ThreadContext;
72class Request;
73
74/**
75 * CheckerCPU class. Dynamically verifies instructions as they are
76 * completed by making sure that the instruction and its results match
77 * the independent execution of the benchmark inside the checker. The
78 * checker verifies instructions in order, regardless of the order in
79 * which instructions complete. There are certain results that can
80 * not be verified, specifically the result of a store conditional or
81 * the values of uncached accesses. In these cases, and with
82 * instructions marked as "IsUnverifiable", the checker assumes that
83 * the value from the main CPU's execution is correct and simply
84 * copies that value. It provides a CheckerThreadContext (see
85 * checker/thread_context.hh) that provides hooks for updating the
86 * Checker's state through any ThreadContext accesses. This allows the
87 * checker to be able to correctly verify instructions, even with
88 * external accesses to the ThreadContext that change state.
89 */
90class CheckerCPU : public BaseCPU, public ExecContext
91{
92 protected:
93 typedef TheISA::MachInst MachInst;
94 typedef TheISA::FloatReg FloatReg;
95 typedef TheISA::FloatRegBits FloatRegBits;
96 typedef TheISA::MiscReg MiscReg;
|
97 typedef TheISA::VectorReg VectorReg;
| |
98
99 /** id attached to all issued requests */
100 MasterID masterId;
101 public:
102 virtual void init();
103
104 typedef CheckerCPUParams Params;
105 CheckerCPU(Params *p);
106 virtual ~CheckerCPU();
107
108 void setSystem(System *system);
109
110 void setIcachePort(MasterPort *icache_port);
111
112 void setDcachePort(MasterPort *dcache_port);
113
114 MasterPort &getDataPort()
115 {
116 // the checker does not have ports on its own so return the
117 // data port of the actual CPU core
118 assert(dcachePort);
119 return *dcachePort;
120 }
121
122 MasterPort &getInstPort()
123 {
124 // the checker does not have ports on its own so return the
125 // data port of the actual CPU core
126 assert(icachePort);
127 return *icachePort;
128 }
129
130 protected:
131
132 std::vector<Process*> workload;
133
134 System *systemPtr;
135
136 MasterPort *icachePort;
137 MasterPort *dcachePort;
138
139 ThreadContext *tc;
140
141 TheISA::TLB *itb;
142 TheISA::TLB *dtb;
143
144 Addr dbg_vtophys(Addr addr);
145
146 union Result {
147 uint64_t integer;
148 double dbl;
| 97
98 /** id attached to all issued requests */
99 MasterID masterId;
100 public:
101 virtual void init();
102
103 typedef CheckerCPUParams Params;
104 CheckerCPU(Params *p);
105 virtual ~CheckerCPU();
106
107 void setSystem(System *system);
108
109 void setIcachePort(MasterPort *icache_port);
110
111 void setDcachePort(MasterPort *dcache_port);
112
113 MasterPort &getDataPort()
114 {
115 // the checker does not have ports on its own so return the
116 // data port of the actual CPU core
117 assert(dcachePort);
118 return *dcachePort;
119 }
120
121 MasterPort &getInstPort()
122 {
123 // the checker does not have ports on its own so return the
124 // data port of the actual CPU core
125 assert(icachePort);
126 return *icachePort;
127 }
128
129 protected:
130
131 std::vector<Process*> workload;
132
133 System *systemPtr;
134
135 MasterPort *icachePort;
136 MasterPort *dcachePort;
137
138 ThreadContext *tc;
139
140 TheISA::TLB *itb;
141 TheISA::TLB *dtb;
142
143 Addr dbg_vtophys(Addr addr);
144
145 union Result {
146 uint64_t integer;
147 double dbl;
|
149
150 // I am assuming that vector register type is different from the two
151 // types used above. Else it seems useless to have a separate typedef
152 // for vector registers.
153 VectorReg vector;
154
| |
155 void set(uint64_t i) { integer = i; }
156 void set(double d) { dbl = d; }
| 148 void set(uint64_t i) { integer = i; }
149 void set(double d) { dbl = d; }
|
157 void set(const VectorReg &v) { vector = v; }
158
| |
159 void get(uint64_t& i) { i = integer; }
160 void get(double& d) { d = dbl; }
| 150 void get(uint64_t& i) { i = integer; }
151 void get(double& d) { d = dbl; }
|
161 void get(VectorReg& v) { v = vector; }
| |
162 };
163
164 // ISAs like ARM can have multiple destination registers to check,
165 // keep them all in a std::queue
166 std::queue<Result> result;
167
168 // Pointer to the one memory request.
169 RequestPtr memReq;
170
171 StaticInstPtr curStaticInst;
172 StaticInstPtr curMacroStaticInst;
173
174 // number of simulated instructions
175 Counter numInst;
176 Counter startNumInst;
177
178 std::queue<int> miscRegIdxs;
179
180 public:
181
182 // Primary thread being run.
183 SimpleThread *thread;
184
185 TheISA::TLB* getITBPtr() { return itb; }
186 TheISA::TLB* getDTBPtr() { return dtb; }
187
188 virtual Counter totalInsts() const
189 {
190 return 0;
191 }
192
193 virtual Counter totalOps() const
194 {
195 return 0;
196 }
197
198 // number of simulated loads
199 Counter numLoad;
200 Counter startNumLoad;
201
202 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
203 void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
204
205 // These functions are only used in CPU models that split
206 // effective address computation from the actual memory access.
207 void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); }
208 Addr getEA() const { panic("SimpleCPU::getEA() not implemented\n"); }
209
210 // The register accessor methods provide the index of the
211 // instruction's operand (e.g., 0 or 1), not the architectural
212 // register index, to simplify the implementation of register
213 // renaming. We find the architectural register index by indexing
214 // into the instruction's own operand index table. Note that a
215 // raw pointer to the StaticInst is provided instead of a
216 // ref-counted StaticInstPtr to redice overhead. This is fine as
217 // long as these methods don't copy the pointer into any long-term
218 // storage (which is pretty hard to imagine they would have reason
219 // to do).
220
221 IntReg readIntRegOperand(const StaticInst *si, int idx)
222 {
223 return thread->readIntReg(si->srcRegIdx(idx));
224 }
225
226 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
227 {
228 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
229 return thread->readFloatReg(reg_idx);
230 }
231
232 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
233 {
234 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
235 return thread->readFloatRegBits(reg_idx);
236 }
237
238 CCReg readCCRegOperand(const StaticInst *si, int idx)
239 {
240 int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
241 return thread->readCCReg(reg_idx);
242 }
243
| 152 };
153
154 // ISAs like ARM can have multiple destination registers to check,
155 // keep them all in a std::queue
156 std::queue<Result> result;
157
158 // Pointer to the one memory request.
159 RequestPtr memReq;
160
161 StaticInstPtr curStaticInst;
162 StaticInstPtr curMacroStaticInst;
163
164 // number of simulated instructions
165 Counter numInst;
166 Counter startNumInst;
167
168 std::queue<int> miscRegIdxs;
169
170 public:
171
172 // Primary thread being run.
173 SimpleThread *thread;
174
175 TheISA::TLB* getITBPtr() { return itb; }
176 TheISA::TLB* getDTBPtr() { return dtb; }
177
178 virtual Counter totalInsts() const
179 {
180 return 0;
181 }
182
183 virtual Counter totalOps() const
184 {
185 return 0;
186 }
187
188 // number of simulated loads
189 Counter numLoad;
190 Counter startNumLoad;
191
192 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
193 void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
194
195 // These functions are only used in CPU models that split
196 // effective address computation from the actual memory access.
197 void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); }
198 Addr getEA() const { panic("SimpleCPU::getEA() not implemented\n"); }
199
200 // The register accessor methods provide the index of the
201 // instruction's operand (e.g., 0 or 1), not the architectural
202 // register index, to simplify the implementation of register
203 // renaming. We find the architectural register index by indexing
204 // into the instruction's own operand index table. Note that a
205 // raw pointer to the StaticInst is provided instead of a
206 // ref-counted StaticInstPtr to redice overhead. This is fine as
207 // long as these methods don't copy the pointer into any long-term
208 // storage (which is pretty hard to imagine they would have reason
209 // to do).
210
211 IntReg readIntRegOperand(const StaticInst *si, int idx)
212 {
213 return thread->readIntReg(si->srcRegIdx(idx));
214 }
215
216 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
217 {
218 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
219 return thread->readFloatReg(reg_idx);
220 }
221
222 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
223 {
224 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
225 return thread->readFloatRegBits(reg_idx);
226 }
227
228 CCReg readCCRegOperand(const StaticInst *si, int idx)
229 {
230 int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
231 return thread->readCCReg(reg_idx);
232 }
233
|
244 const VectorReg &readVectorRegOperand(const StaticInst *si, int idx)
245 {
246 return thread->readVectorReg(si->srcRegIdx(idx));
247 }
248
| |
249 template <class T>
250 void setResult(T t)
251 {
252 Result instRes;
253 instRes.set(t);
254 result.push(instRes);
255 }
256
257 void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
258 {
259 thread->setIntReg(si->destRegIdx(idx), val);
260 setResult<uint64_t>(val);
261 }
262
263 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
264 {
265 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
266 thread->setFloatReg(reg_idx, val);
267 setResult<double>(val);
268 }
269
270 void setFloatRegOperandBits(const StaticInst *si, int idx,
271 FloatRegBits val)
272 {
273 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
274 thread->setFloatRegBits(reg_idx, val);
275 setResult<uint64_t>(val);
276 }
277
278 void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
279 {
280 int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base;
281 thread->setCCReg(reg_idx, val);
282 setResult<uint64_t>(val);
283 }
284
| 234 template <class T>
235 void setResult(T t)
236 {
237 Result instRes;
238 instRes.set(t);
239 result.push(instRes);
240 }
241
242 void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
243 {
244 thread->setIntReg(si->destRegIdx(idx), val);
245 setResult<uint64_t>(val);
246 }
247
248 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
249 {
250 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
251 thread->setFloatReg(reg_idx, val);
252 setResult<double>(val);
253 }
254
255 void setFloatRegOperandBits(const StaticInst *si, int idx,
256 FloatRegBits val)
257 {
258 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
259 thread->setFloatRegBits(reg_idx, val);
260 setResult<uint64_t>(val);
261 }
262
263 void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
264 {
265 int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base;
266 thread->setCCReg(reg_idx, val);
267 setResult<uint64_t>(val);
268 }
269
|
285 void setVectorRegOperand(const StaticInst *si, int idx,
286 const VectorReg &val)
287 {
288 thread->setVectorReg(si->destRegIdx(idx), val);
289 setResult<VectorReg>(val);
290 }
291
| |
292 bool readPredicate() { return thread->readPredicate(); }
293 void setPredicate(bool val)
294 {
295 thread->setPredicate(val);
296 }
297
298 TheISA::PCState pcState() const { return thread->pcState(); }
299 void pcState(const TheISA::PCState &val)
300 {
301 DPRINTF(Checker, "Changing PC to %s, old PC %s.\n",
302 val, thread->pcState());
303 thread->pcState(val);
304 }
305 Addr instAddr() { return thread->instAddr(); }
306 Addr nextInstAddr() { return thread->nextInstAddr(); }
307 MicroPC microPC() { return thread->microPC(); }
308 //////////////////////////////////////////
309
310 MiscReg readMiscRegNoEffect(int misc_reg) const
311 {
312 return thread->readMiscRegNoEffect(misc_reg);
313 }
314
315 MiscReg readMiscReg(int misc_reg)
316 {
317 return thread->readMiscReg(misc_reg);
318 }
319
320 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
321 {
322 DPRINTF(Checker, "Setting misc reg %d with no effect to check later\n", misc_reg);
323 miscRegIdxs.push(misc_reg);
324 return thread->setMiscRegNoEffect(misc_reg, val);
325 }
326
327 void setMiscReg(int misc_reg, const MiscReg &val)
328 {
329 DPRINTF(Checker, "Setting misc reg %d with effect to check later\n", misc_reg);
330 miscRegIdxs.push(misc_reg);
331 return thread->setMiscReg(misc_reg, val);
332 }
333
334 MiscReg readMiscRegOperand(const StaticInst *si, int idx)
335 {
336 int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
337 return thread->readMiscReg(reg_idx);
338 }
339
340 void setMiscRegOperand(
341 const StaticInst *si, int idx, const MiscReg &val)
342 {
343 int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
344 return this->setMiscReg(reg_idx, val);
345 }
346
347#if THE_ISA == MIPS_ISA
348 MiscReg readRegOtherThread(int misc_reg, ThreadID tid)
349 {
350 panic("MIPS MT not defined for CheckerCPU.\n");
351 return 0;
352 }
353
354 void setRegOtherThread(int misc_reg, MiscReg val, ThreadID tid)
355 {
356 panic("MIPS MT not defined for CheckerCPU.\n");
357 }
358#endif
359
360 /////////////////////////////////////////
361
362 void recordPCChange(const TheISA::PCState &val)
363 {
364 changedPC = true;
365 newPCState = val;
366 }
367
368 void demapPage(Addr vaddr, uint64_t asn)
369 {
370 this->itb->demapPage(vaddr, asn);
371 this->dtb->demapPage(vaddr, asn);
372 }
373
374 // monitor/mwait funtions
375 virtual void armMonitor(Addr address) { BaseCPU::armMonitor(address); }
376 bool mwait(PacketPtr pkt) { return BaseCPU::mwait(pkt); }
377 void mwaitAtomic(ThreadContext *tc)
378 { return BaseCPU::mwaitAtomic(tc, thread->dtb); }
379 AddressMonitor *getAddrMonitor() { return BaseCPU::getCpuAddrMonitor(); }
380
381 void demapInstPage(Addr vaddr, uint64_t asn)
382 {
383 this->itb->demapPage(vaddr, asn);
384 }
385
386 void demapDataPage(Addr vaddr, uint64_t asn)
387 {
388 this->dtb->demapPage(vaddr, asn);
389 }
390
391 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
392 Fault writeMem(uint8_t *data, unsigned size,
393 Addr addr, unsigned flags, uint64_t *res);
394
395 unsigned int readStCondFailures() const {
396 return thread->readStCondFailures();
397 }
398
399 void setStCondFailures(unsigned int sc_failures)
400 {}
401 /////////////////////////////////////////////////////
402
403 Fault hwrei() { return thread->hwrei(); }
404 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
405 void wakeup() { }
406 // Assume that the normal CPU's call to syscall was successful.
407 // The checker's state would have already been updated by the syscall.
408 void syscall(int64_t callnum) { }
409
410 void handleError()
411 {
412 if (exitOnError)
413 dumpAndExit();
414 }
415
416 bool checkFlags(Request *unverified_req, Addr vAddr,
417 Addr pAddr, int flags);
418
419 void dumpAndExit();
420
421 ThreadContext *tcBase() { return tc; }
422 SimpleThread *threadBase() { return thread; }
423
424 Result unverifiedResult;
425 Request *unverifiedReq;
426 uint8_t *unverifiedMemData;
427
428 bool changedPC;
429 bool willChangePC;
430 TheISA::PCState newPCState;
431 bool exitOnError;
432 bool updateOnError;
433 bool warnOnlyOnLoadError;
434
435 InstSeqNum youngestSN;
436};
437
438/**
439 * Templated Checker class. This Checker class is templated on the
440 * DynInstPtr of the instruction type that will be verified. Proper
441 * template instantiations of the Checker must be placed at the bottom
442 * of checker/cpu.cc.
443 */
444template <class Impl>
445class Checker : public CheckerCPU
446{
447 private:
448 typedef typename Impl::DynInstPtr DynInstPtr;
449
450 public:
451 Checker(Params *p)
452 : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL)
453 { }
454
455 void switchOut();
456 void takeOverFrom(BaseCPU *oldCPU);
457
458 void advancePC(const Fault &fault);
459
460 void verify(DynInstPtr &inst);
461
462 void validateInst(DynInstPtr &inst);
463 void validateExecution(DynInstPtr &inst);
464 void validateState();
465
| 270 bool readPredicate() { return thread->readPredicate(); }
271 void setPredicate(bool val)
272 {
273 thread->setPredicate(val);
274 }
275
276 TheISA::PCState pcState() const { return thread->pcState(); }
277 void pcState(const TheISA::PCState &val)
278 {
279 DPRINTF(Checker, "Changing PC to %s, old PC %s.\n",
280 val, thread->pcState());
281 thread->pcState(val);
282 }
283 Addr instAddr() { return thread->instAddr(); }
284 Addr nextInstAddr() { return thread->nextInstAddr(); }
285 MicroPC microPC() { return thread->microPC(); }
286 //////////////////////////////////////////
287
288 MiscReg readMiscRegNoEffect(int misc_reg) const
289 {
290 return thread->readMiscRegNoEffect(misc_reg);
291 }
292
293 MiscReg readMiscReg(int misc_reg)
294 {
295 return thread->readMiscReg(misc_reg);
296 }
297
298 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
299 {
300 DPRINTF(Checker, "Setting misc reg %d with no effect to check later\n", misc_reg);
301 miscRegIdxs.push(misc_reg);
302 return thread->setMiscRegNoEffect(misc_reg, val);
303 }
304
305 void setMiscReg(int misc_reg, const MiscReg &val)
306 {
307 DPRINTF(Checker, "Setting misc reg %d with effect to check later\n", misc_reg);
308 miscRegIdxs.push(misc_reg);
309 return thread->setMiscReg(misc_reg, val);
310 }
311
312 MiscReg readMiscRegOperand(const StaticInst *si, int idx)
313 {
314 int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
315 return thread->readMiscReg(reg_idx);
316 }
317
318 void setMiscRegOperand(
319 const StaticInst *si, int idx, const MiscReg &val)
320 {
321 int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
322 return this->setMiscReg(reg_idx, val);
323 }
324
325#if THE_ISA == MIPS_ISA
326 MiscReg readRegOtherThread(int misc_reg, ThreadID tid)
327 {
328 panic("MIPS MT not defined for CheckerCPU.\n");
329 return 0;
330 }
331
332 void setRegOtherThread(int misc_reg, MiscReg val, ThreadID tid)
333 {
334 panic("MIPS MT not defined for CheckerCPU.\n");
335 }
336#endif
337
338 /////////////////////////////////////////
339
340 void recordPCChange(const TheISA::PCState &val)
341 {
342 changedPC = true;
343 newPCState = val;
344 }
345
346 void demapPage(Addr vaddr, uint64_t asn)
347 {
348 this->itb->demapPage(vaddr, asn);
349 this->dtb->demapPage(vaddr, asn);
350 }
351
352 // monitor/mwait funtions
353 virtual void armMonitor(Addr address) { BaseCPU::armMonitor(address); }
354 bool mwait(PacketPtr pkt) { return BaseCPU::mwait(pkt); }
355 void mwaitAtomic(ThreadContext *tc)
356 { return BaseCPU::mwaitAtomic(tc, thread->dtb); }
357 AddressMonitor *getAddrMonitor() { return BaseCPU::getCpuAddrMonitor(); }
358
359 void demapInstPage(Addr vaddr, uint64_t asn)
360 {
361 this->itb->demapPage(vaddr, asn);
362 }
363
364 void demapDataPage(Addr vaddr, uint64_t asn)
365 {
366 this->dtb->demapPage(vaddr, asn);
367 }
368
369 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
370 Fault writeMem(uint8_t *data, unsigned size,
371 Addr addr, unsigned flags, uint64_t *res);
372
373 unsigned int readStCondFailures() const {
374 return thread->readStCondFailures();
375 }
376
377 void setStCondFailures(unsigned int sc_failures)
378 {}
379 /////////////////////////////////////////////////////
380
381 Fault hwrei() { return thread->hwrei(); }
382 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
383 void wakeup() { }
384 // Assume that the normal CPU's call to syscall was successful.
385 // The checker's state would have already been updated by the syscall.
386 void syscall(int64_t callnum) { }
387
388 void handleError()
389 {
390 if (exitOnError)
391 dumpAndExit();
392 }
393
394 bool checkFlags(Request *unverified_req, Addr vAddr,
395 Addr pAddr, int flags);
396
397 void dumpAndExit();
398
399 ThreadContext *tcBase() { return tc; }
400 SimpleThread *threadBase() { return thread; }
401
402 Result unverifiedResult;
403 Request *unverifiedReq;
404 uint8_t *unverifiedMemData;
405
406 bool changedPC;
407 bool willChangePC;
408 TheISA::PCState newPCState;
409 bool exitOnError;
410 bool updateOnError;
411 bool warnOnlyOnLoadError;
412
413 InstSeqNum youngestSN;
414};
415
416/**
417 * Templated Checker class. This Checker class is templated on the
418 * DynInstPtr of the instruction type that will be verified. Proper
419 * template instantiations of the Checker must be placed at the bottom
420 * of checker/cpu.cc.
421 */
422template <class Impl>
423class Checker : public CheckerCPU
424{
425 private:
426 typedef typename Impl::DynInstPtr DynInstPtr;
427
428 public:
429 Checker(Params *p)
430 : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL)
431 { }
432
433 void switchOut();
434 void takeOverFrom(BaseCPU *oldCPU);
435
436 void advancePC(const Fault &fault);
437
438 void verify(DynInstPtr &inst);
439
440 void validateInst(DynInstPtr &inst);
441 void validateExecution(DynInstPtr &inst);
442 void validateState();
443
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466 void copyResult(DynInstPtr &inst, Result mismatch_val, int start_idx);
| 444 void copyResult(DynInstPtr &inst, uint64_t mismatch_val, int start_idx);
|
467 void handlePendingInt();
468
469 private:
470 void handleError(DynInstPtr &inst)
471 {
472 if (exitOnError) {
473 dumpAndExit(inst);
474 } else if (updateOnError) {
475 updateThisCycle = true;
476 }
477 }
478
479 void dumpAndExit(DynInstPtr &inst);
480
481 bool updateThisCycle;
482
483 DynInstPtr unverifiedInst;
484
485 std::list<DynInstPtr> instList;
486 typedef typename std::list<DynInstPtr>::iterator InstListIt;
487 void dumpInsts();
488};
489
490#endif // __CPU_CHECKER_CPU_HH__
| 445 void handlePendingInt();
446
447 private:
448 void handleError(DynInstPtr &inst)
449 {
450 if (exitOnError) {
451 dumpAndExit(inst);
452 } else if (updateOnError) {
453 updateThisCycle = true;
454 }
455 }
456
457 void dumpAndExit(DynInstPtr &inst);
458
459 bool updateThisCycle;
460
461 DynInstPtr unverifiedInst;
462
463 std::list<DynInstPtr> instList;
464 typedef typename std::list<DynInstPtr>::iterator InstListIt;
465 void dumpInsts();
466};
467
468#endif // __CPU_CHECKER_CPU_HH__
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