cpu.hh (12106:7784fac1b159) | cpu.hh (12107:998b4c54ee51) |
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1/* | 1/* |
2 * Copyright (c) 2011 ARM Limited | 2 * Copyright (c) 2011, 2016 ARM Limited |
3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license --- 37 unchanged lines hidden (view full) --- 48#include <map> 49#include <queue> 50 51#include "arch/types.hh" 52#include "base/statistics.hh" 53#include "cpu/base.hh" 54#include "cpu/base_dyn_inst.hh" 55#include "cpu/exec_context.hh" | 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license --- 37 unchanged lines hidden (view full) --- 48#include <map> 49#include <queue> 50 51#include "arch/types.hh" 52#include "base/statistics.hh" 53#include "cpu/base.hh" 54#include "cpu/base_dyn_inst.hh" 55#include "cpu/exec_context.hh" |
56#include "cpu/inst_res.hh" |
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56#include "cpu/pc_event.hh" 57#include "cpu/simple_thread.hh" 58#include "cpu/static_inst.hh" 59#include "debug/Checker.hh" 60#include "mem/request.hh" 61#include "params/CheckerCPU.hh" 62#include "sim/eventq.hh" 63 --- 74 unchanged lines hidden (view full) --- 138 139 ThreadContext *tc; 140 141 TheISA::TLB *itb; 142 TheISA::TLB *dtb; 143 144 Addr dbg_vtophys(Addr addr); 145 | 57#include "cpu/pc_event.hh" 58#include "cpu/simple_thread.hh" 59#include "cpu/static_inst.hh" 60#include "debug/Checker.hh" 61#include "mem/request.hh" 62#include "params/CheckerCPU.hh" 63#include "sim/eventq.hh" 64 --- 74 unchanged lines hidden (view full) --- 139 140 ThreadContext *tc; 141 142 TheISA::TLB *itb; 143 TheISA::TLB *dtb; 144 145 Addr dbg_vtophys(Addr addr); 146 |
146 union Result { 147 uint64_t integer; 148 double dbl; 149 void set(uint64_t i) { integer = i; } 150 void set(double d) { dbl = d; } 151 void get(uint64_t& i) { i = integer; } 152 void get(double& d) { d = dbl; } 153 }; 154 | |
155 // ISAs like ARM can have multiple destination registers to check, 156 // keep them all in a std::queue | 147 // ISAs like ARM can have multiple destination registers to check, 148 // keep them all in a std::queue |
157 std::queue | 149 std::queue<InstResult> result; |
158 159 // Pointer to the one memory request. 160 RequestPtr memReq; 161 162 StaticInstPtr curStaticInst; 163 StaticInstPtr curMacroStaticInst; 164 165 // number of simulated instructions --- 69 unchanged lines hidden (view full) --- 235 236 CCReg readCCRegOperand(const StaticInst *si, int idx) override 237 { 238 const RegId& reg = si->srcRegIdx(idx); 239 assert(reg.isCCReg()); 240 return thread->readCCReg(reg.index()); 241 } 242 | 150 151 // Pointer to the one memory request. 152 RequestPtr memReq; 153 154 StaticInstPtr curStaticInst; 155 StaticInstPtr curMacroStaticInst; 156 157 // number of simulated instructions --- 69 unchanged lines hidden (view full) --- 227 228 CCReg readCCRegOperand(const StaticInst *si, int idx) override 229 { 230 const RegId& reg = si->srcRegIdx(idx); 231 assert(reg.isCCReg()); 232 return thread->readCCReg(reg.index()); 233 } 234 |
243 template <class T> 244 void setResult(T t) | 235 template<typename T> 236 void setScalarResult(T&& t) |
245 { | 237 { |
246 Result instRes; 247 instRes.set(t); 248 result.push(instRes); | 238 result.push(InstResult(std::forward<T>(t), 239 InstResult::ResultType::Scalar)); |
249 } 250 251 void setIntRegOperand(const StaticInst *si, int idx, 252 IntReg val) override 253 { 254 const RegId& reg = si->destRegIdx(idx); 255 assert(reg.isIntReg()); 256 thread->setIntReg(reg.index(), val); | 240 } 241 242 void setIntRegOperand(const StaticInst *si, int idx, 243 IntReg val) override 244 { 245 const RegId& reg = si->destRegIdx(idx); 246 assert(reg.isIntReg()); 247 thread->setIntReg(reg.index(), val); |
257 setResult<uint64_t>(val); | 248 setScalarResult(val); |
258 } 259 260 void setFloatRegOperand(const StaticInst *si, int idx, 261 FloatReg val) override 262 { 263 const RegId& reg = si->destRegIdx(idx); 264 assert(reg.isFloatReg()); 265 thread->setFloatReg(reg.index(), val); | 249 } 250 251 void setFloatRegOperand(const StaticInst *si, int idx, 252 FloatReg val) override 253 { 254 const RegId& reg = si->destRegIdx(idx); 255 assert(reg.isFloatReg()); 256 thread->setFloatReg(reg.index(), val); |
266 setResult<double>(val); | 257 setScalarResult(val); |
267 } 268 269 void setFloatRegOperandBits(const StaticInst *si, int idx, 270 FloatRegBits val) override 271 { 272 const RegId& reg = si->destRegIdx(idx); 273 assert(reg.isFloatReg()); 274 thread->setFloatRegBits(reg.index(), val); | 258 } 259 260 void setFloatRegOperandBits(const StaticInst *si, int idx, 261 FloatRegBits val) override 262 { 263 const RegId& reg = si->destRegIdx(idx); 264 assert(reg.isFloatReg()); 265 thread->setFloatRegBits(reg.index(), val); |
275 setResult<uint64_t>(val); | 266 setScalarResult(val); |
276 } 277 278 void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override 279 { 280 const RegId& reg = si->destRegIdx(idx); 281 assert(reg.isCCReg()); 282 thread->setCCReg(reg.index(), val); | 267 } 268 269 void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override 270 { 271 const RegId& reg = si->destRegIdx(idx); 272 assert(reg.isCCReg()); 273 thread->setCCReg(reg.index(), val); |
283 setResult<uint64_t>(val); | 274 setScalarResult((uint64_t)val); |
284 } 285 286 bool readPredicate() override { return thread->readPredicate(); } 287 void setPredicate(bool val) override 288 { 289 thread->setPredicate(val); 290 } 291 --- 125 unchanged lines hidden (view full) --- 417 bool checkFlags(Request *unverified_req, Addr vAddr, 418 Addr pAddr, int flags); 419 420 void dumpAndExit(); 421 422 ThreadContext *tcBase() override { return tc; } 423 SimpleThread *threadBase() { return thread; } 424 | 275 } 276 277 bool readPredicate() override { return thread->readPredicate(); } 278 void setPredicate(bool val) override 279 { 280 thread->setPredicate(val); 281 } 282 --- 125 unchanged lines hidden (view full) --- 408 bool checkFlags(Request *unverified_req, Addr vAddr, 409 Addr pAddr, int flags); 410 411 void dumpAndExit(); 412 413 ThreadContext *tcBase() override { return tc; } 414 SimpleThread *threadBase() { return thread; } 415 |
425 Result unverifiedResult; | 416 InstResult unverifiedResult; |
426 Request *unverifiedReq; 427 uint8_t *unverifiedMemData; 428 429 bool changedPC; 430 bool willChangePC; 431 TheISA::PCState newPCState; 432 bool exitOnError; 433 bool updateOnError; --- 25 unchanged lines hidden (view full) --- 459 void advancePC(const Fault &fault); 460 461 void verify(DynInstPtr &inst); 462 463 void validateInst(DynInstPtr &inst); 464 void validateExecution(DynInstPtr &inst); 465 void validateState(); 466 | 417 Request *unverifiedReq; 418 uint8_t *unverifiedMemData; 419 420 bool changedPC; 421 bool willChangePC; 422 TheISA::PCState newPCState; 423 bool exitOnError; 424 bool updateOnError; --- 25 unchanged lines hidden (view full) --- 450 void advancePC(const Fault &fault); 451 452 void verify(DynInstPtr &inst); 453 454 void validateInst(DynInstPtr &inst); 455 void validateExecution(DynInstPtr &inst); 456 void validateState(); 457 |
467 void copyResult(DynInstPtr &inst, uint64_t mismatch_val, int start_idx); | 458 void copyResult(DynInstPtr &inst, const InstResult& mismatch_val, 459 int start_idx); |
468 void handlePendingInt(); 469 470 private: 471 void handleError(DynInstPtr &inst) 472 { 473 if (exitOnError) { 474 dumpAndExit(inst); 475 } else if (updateOnError) { --- 16 unchanged lines hidden --- | 460 void handlePendingInt(); 461 462 private: 463 void handleError(DynInstPtr &inst) 464 { 465 if (exitOnError) { 466 dumpAndExit(inst); 467 } else if (updateOnError) { --- 16 unchanged lines hidden --- |