cpu.hh (10934:5af8f40d8f2c) | cpu.hh (10935:acd48ddd725f) |
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1/* 2 * Copyright (c) 2011 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 80 unchanged lines hidden (view full) --- 89 */ 90class CheckerCPU : public BaseCPU, public ExecContext 91{ 92 protected: 93 typedef TheISA::MachInst MachInst; 94 typedef TheISA::FloatReg FloatReg; 95 typedef TheISA::FloatRegBits FloatRegBits; 96 typedef TheISA::MiscReg MiscReg; | 1/* 2 * Copyright (c) 2011 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 80 unchanged lines hidden (view full) --- 89 */ 90class CheckerCPU : public BaseCPU, public ExecContext 91{ 92 protected: 93 typedef TheISA::MachInst MachInst; 94 typedef TheISA::FloatReg FloatReg; 95 typedef TheISA::FloatRegBits FloatRegBits; 96 typedef TheISA::MiscReg MiscReg; |
97 typedef TheISA::VectorReg VectorReg; | |
98 99 /** id attached to all issued requests */ 100 MasterID masterId; 101 public: 102 virtual void init(); 103 104 typedef CheckerCPUParams Params; 105 CheckerCPU(Params *p); --- 35 unchanged lines hidden (view full) --- 141 TheISA::TLB *itb; 142 TheISA::TLB *dtb; 143 144 Addr dbg_vtophys(Addr addr); 145 146 union Result { 147 uint64_t integer; 148 double dbl; | 97 98 /** id attached to all issued requests */ 99 MasterID masterId; 100 public: 101 virtual void init(); 102 103 typedef CheckerCPUParams Params; 104 CheckerCPU(Params *p); --- 35 unchanged lines hidden (view full) --- 140 TheISA::TLB *itb; 141 TheISA::TLB *dtb; 142 143 Addr dbg_vtophys(Addr addr); 144 145 union Result { 146 uint64_t integer; 147 double dbl; |
149 150 // I am assuming that vector register type is different from the two 151 // types used above. Else it seems useless to have a separate typedef 152 // for vector registers. 153 VectorReg vector; 154 | |
155 void set(uint64_t i) { integer = i; } 156 void set(double d) { dbl = d; } | 148 void set(uint64_t i) { integer = i; } 149 void set(double d) { dbl = d; } |
157 void set(const VectorReg &v) { vector = v; } 158 | |
159 void get(uint64_t& i) { i = integer; } 160 void get(double& d) { d = dbl; } | 150 void get(uint64_t& i) { i = integer; } 151 void get(double& d) { d = dbl; } |
161 void get(VectorReg& v) { v = vector; } | |
162 }; 163 164 // ISAs like ARM can have multiple destination registers to check, 165 // keep them all in a std::queue 166 std::queue<Result> result; 167 168 // Pointer to the one memory request. 169 RequestPtr memReq; --- 66 unchanged lines hidden (view full) --- 236 } 237 238 CCReg readCCRegOperand(const StaticInst *si, int idx) 239 { 240 int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base; 241 return thread->readCCReg(reg_idx); 242 } 243 | 152 }; 153 154 // ISAs like ARM can have multiple destination registers to check, 155 // keep them all in a std::queue 156 std::queue<Result> result; 157 158 // Pointer to the one memory request. 159 RequestPtr memReq; --- 66 unchanged lines hidden (view full) --- 226 } 227 228 CCReg readCCRegOperand(const StaticInst *si, int idx) 229 { 230 int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base; 231 return thread->readCCReg(reg_idx); 232 } 233 |
244 const VectorReg &readVectorRegOperand(const StaticInst *si, int idx) 245 { 246 return thread->readVectorReg(si->srcRegIdx(idx)); 247 } 248 | |
249 template <class T> 250 void setResult(T t) 251 { 252 Result instRes; 253 instRes.set(t); 254 result.push(instRes); 255 } 256 --- 20 unchanged lines hidden (view full) --- 277 278 void setCCRegOperand(const StaticInst *si, int idx, CCReg val) 279 { 280 int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base; 281 thread->setCCReg(reg_idx, val); 282 setResult<uint64_t>(val); 283 } 284 | 234 template <class T> 235 void setResult(T t) 236 { 237 Result instRes; 238 instRes.set(t); 239 result.push(instRes); 240 } 241 --- 20 unchanged lines hidden (view full) --- 262 263 void setCCRegOperand(const StaticInst *si, int idx, CCReg val) 264 { 265 int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base; 266 thread->setCCReg(reg_idx, val); 267 setResult<uint64_t>(val); 268 } 269 |
285 void setVectorRegOperand(const StaticInst *si, int idx, 286 const VectorReg &val) 287 { 288 thread->setVectorReg(si->destRegIdx(idx), val); 289 setResult<VectorReg>(val); 290 } 291 | |
292 bool readPredicate() { return thread->readPredicate(); } 293 void setPredicate(bool val) 294 { 295 thread->setPredicate(val); 296 } 297 298 TheISA::PCState pcState() const { return thread->pcState(); } 299 void pcState(const TheISA::PCState &val) --- 158 unchanged lines hidden (view full) --- 458 void advancePC(const Fault &fault); 459 460 void verify(DynInstPtr &inst); 461 462 void validateInst(DynInstPtr &inst); 463 void validateExecution(DynInstPtr &inst); 464 void validateState(); 465 | 270 bool readPredicate() { return thread->readPredicate(); } 271 void setPredicate(bool val) 272 { 273 thread->setPredicate(val); 274 } 275 276 TheISA::PCState pcState() const { return thread->pcState(); } 277 void pcState(const TheISA::PCState &val) --- 158 unchanged lines hidden (view full) --- 436 void advancePC(const Fault &fault); 437 438 void verify(DynInstPtr &inst); 439 440 void validateInst(DynInstPtr &inst); 441 void validateExecution(DynInstPtr &inst); 442 void validateState(); 443 |
466 void copyResult(DynInstPtr &inst, Result mismatch_val, int start_idx); | 444 void copyResult(DynInstPtr &inst, uint64_t mismatch_val, int start_idx); |
467 void handlePendingInt(); 468 469 private: 470 void handleError(DynInstPtr &inst) 471 { 472 if (exitOnError) { 473 dumpAndExit(inst); 474 } else if (updateOnError) { --- 16 unchanged lines hidden --- | 445 void handlePendingInt(); 446 447 private: 448 void handleError(DynInstPtr &inst) 449 { 450 if (exitOnError) { 451 dumpAndExit(inst); 452 } else if (updateOnError) { --- 16 unchanged lines hidden --- |