1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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93 typedef TheISA::FloatRegBits FloatRegBits;
94 typedef TheISA::MiscReg MiscReg;
95
96 /** id attached to all issued requests */
97 MasterID masterId;
98 public:
99 virtual void init();
100
101 public:
102 typedef CheckerCPUParams Params;
103 const Params *params() const
104 { return reinterpret_cast<const Params *>(_params); }
105 CheckerCPU(Params *p);
106 virtual ~CheckerCPU();
107
108 std::vector<Process*> workload;
109
110 void setSystem(System *system);
111
112 System *systemPtr;
113
114 void setIcachePort(CpuPort *icache_port);
115
116 CpuPort *icachePort;
117
118 void setDcachePort(CpuPort *dcache_port);
119
120 CpuPort *dcachePort;
121
122 CpuPort &getDataPort()
123 {
124 panic("Not supported on checker!");
125 return *dcachePort;
126 }
127
128 CpuPort &getInstPort()
129 {
130 panic("Not supported on checker!");
131 return *icachePort;
132 }
133
134 public:
135 // Primary thread being run.
136 SimpleThread *thread;
137
138 ThreadContext *tc;
139
140 TheISA::TLB *itb;
141 TheISA::TLB *dtb;
142
143 Addr dbg_vtophys(Addr addr);
144
145 union Result {

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162 StaticInstPtr curMacroStaticInst;
163
164 // number of simulated instructions
165 Counter numInst;
166 Counter startNumInst;
167
168 std::queue<int> miscRegIdxs;
169
170 TheISA::TLB* getITBPtr() { return itb; }
171 TheISA::TLB* getDTBPtr() { return dtb; }
172
173 virtual Counter totalInsts() const
174 {
175 return 0;
176 }
177

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