base_dyn_inst_impl.hh (8545:a3992291e230) base_dyn_inst_impl.hh (8733:64a7bf8fa56c)
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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43#include <iostream>
44#include <set>
45#include <sstream>
46#include <string>
47
48#include "base/cprintf.hh"
49#include "base/trace.hh"
50#include "config/the_isa.hh"
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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43#include <iostream>
44#include <set>
45#include <sstream>
46#include <string>
47
48#include "base/cprintf.hh"
49#include "base/trace.hh"
50#include "config/the_isa.hh"
51#include "config/use_checker.hh"
51#include "cpu/base_dyn_inst.hh"
52#include "cpu/exetrace.hh"
53#include "debug/DynInst.hh"
54#include "debug/IQ.hh"
55#include "mem/request.hh"
56#include "sim/faults.hh"
57
58#define NOHASH

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112 translationCompleted = false;
113 possibleLoadViolation = false;
114 hitExternalSnoop = false;
115
116 isUncacheable = false;
117 reqMade = false;
118 readyRegs = 0;
119
52#include "cpu/base_dyn_inst.hh"
53#include "cpu/exetrace.hh"
54#include "debug/DynInst.hh"
55#include "debug/IQ.hh"
56#include "mem/request.hh"
57#include "sim/faults.hh"
58
59#define NOHASH

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113 translationCompleted = false;
114 possibleLoadViolation = false;
115 hitExternalSnoop = false;
116
117 isUncacheable = false;
118 reqMade = false;
119 readyRegs = 0;
120
120 instResult.integer = 0;
121 recordResult = true;
122
123 status.reset();
124
125 eaCalcDone = false;
126 memOpDone = false;
127 predicate = true;
128

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152 DPRINTF(DynInst,
153 "DynInst: [sn:%lli] Instruction created. Instcount for %s = %i\n",
154 seqNum, cpu->name(), cpu->instcount);
155#endif
156
157#ifdef DEBUG
158 cpu->snList.insert(seqNum);
159#endif
121 recordResult = true;
122
123 status.reset();
124
125 eaCalcDone = false;
126 memOpDone = false;
127 predicate = true;
128

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152 DPRINTF(DynInst,
153 "DynInst: [sn:%lli] Instruction created. Instcount for %s = %i\n",
154 seqNum, cpu->name(), cpu->instcount);
155#endif
156
157#ifdef DEBUG
158 cpu->snList.insert(seqNum);
159#endif
160
161#if USE_CHECKER
162 reqToVerify = NULL;
163#endif
160}
161
162template <class Impl>
163BaseDynInst<Impl>::~BaseDynInst()
164{
165 if (memData) {
166 delete [] memData;
167 }

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177
178 DPRINTF(DynInst,
179 "DynInst: [sn:%lli] Instruction destroyed. Instcount for %s = %i\n",
180 seqNum, cpu->name(), cpu->instcount);
181#endif
182#ifdef DEBUG
183 cpu->snList.erase(seqNum);
184#endif
164}
165
166template <class Impl>
167BaseDynInst<Impl>::~BaseDynInst()
168{
169 if (memData) {
170 delete [] memData;
171 }

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181
182 DPRINTF(DynInst,
183 "DynInst: [sn:%lli] Instruction destroyed. Instcount for %s = %i\n",
184 seqNum, cpu->name(), cpu->instcount);
185#endif
186#ifdef DEBUG
187 cpu->snList.erase(seqNum);
188#endif
189
190#if USE_CHECKER
191 if (reqToVerify)
192 delete reqToVerify;
193#endif // USE_CHECKER
185}
186
187#ifdef DEBUG
188template <class Impl>
189void
190BaseDynInst<Impl>::dumpSNList()
191{
192 std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();

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195
196#ifdef DEBUG
197template <class Impl>
198void
199BaseDynInst<Impl>::dumpSNList()
200{
201 std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();

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