base_dyn_inst_impl.hh (4653:19f884e6a48b) base_dyn_inst_impl.hh (4654:225cc048edfa)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 59 unchanged lines hidden (view full) ---

68 Addr pred_PC, Addr pred_NPC,
69 Addr pred_MicroPC,
70 InstSeqNum seq_num, ImplCPU *cpu)
71 : staticInst(_staticInst), traceData(NULL), cpu(cpu)
72{
73 seqNum = seq_num;
74
75 bool nextIsMicro =
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 59 unchanged lines hidden (view full) ---

68 Addr pred_PC, Addr pred_NPC,
69 Addr pred_MicroPC,
70 InstSeqNum seq_num, ImplCPU *cpu)
71 : staticInst(_staticInst), traceData(NULL), cpu(cpu)
72{
73 seqNum = seq_num;
74
75 bool nextIsMicro =
76 staticInst->isMicroOp() && !staticInst->isLastMicroOp();
76 staticInst->isMicroop() && !staticInst->isLastMicroop();
77
78 PC = inst_PC;
79 microPC = inst_MicroPC;
80 if (nextIsMicro) {
81 nextPC = inst_PC;
82 nextNPC = inst_NPC;
83 nextMicroPC = microPC + 1;
84 } else {

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96
97template <class Impl>
98BaseDynInst<Impl>::BaseDynInst(TheISA::ExtMachInst inst,
99 Addr inst_PC, Addr inst_NPC,
100 Addr inst_MicroPC,
101 Addr pred_PC, Addr pred_NPC,
102 Addr pred_MicroPC,
103 InstSeqNum seq_num, ImplCPU *cpu)
77
78 PC = inst_PC;
79 microPC = inst_MicroPC;
80 if (nextIsMicro) {
81 nextPC = inst_PC;
82 nextNPC = inst_NPC;
83 nextMicroPC = microPC + 1;
84 } else {

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96
97template <class Impl>
98BaseDynInst<Impl>::BaseDynInst(TheISA::ExtMachInst inst,
99 Addr inst_PC, Addr inst_NPC,
100 Addr inst_MicroPC,
101 Addr pred_PC, Addr pred_NPC,
102 Addr pred_MicroPC,
103 InstSeqNum seq_num, ImplCPU *cpu)
104 : staticInst(inst), traceData(NULL), cpu(cpu)
104 : staticInst(inst, inst_PC), traceData(NULL), cpu(cpu)
105{
106 seqNum = seq_num;
107
108 bool nextIsMicro =
105{
106 seqNum = seq_num;
107
108 bool nextIsMicro =
109 staticInst->isMicroOp() && !staticInst->isLastMicroOp();
109 staticInst->isMicroop() && !staticInst->isLastMicroop();
110
111 PC = inst_PC;
112 microPC = inst_MicroPC;
113 if (nextIsMicro) {
114 nextPC = inst_PC;
115 nextNPC = inst_NPC;
116 nextMicroPC = microPC + 1;
117 } else {

--- 229 unchanged lines hidden --- 		110
111 PC = inst_PC;
112 microPC = inst_MicroPC;
113 if (nextIsMicro) {
114 nextPC = inst_PC;
115 nextNPC = inst_NPC;
116 nextMicroPC = microPC + 1;
117 } else {

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