base_dyn_inst_impl.hh (2980:eab855f06b79) base_dyn_inst_impl.hh (3172:2c84db071850)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 179 unchanged lines hidden (view full) ---

188 req->asid = asid;
189
190 // Prefetches never cause faults.
191 fault = NoFault;
192
193 // note this is a local, not BaseDynInst::fault
194 Fault trans_fault = cpu->translateDataReadReq(req);
195
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 179 unchanged lines hidden (view full) ---

188 req->asid = asid;
189
190 // Prefetches never cause faults.
191 fault = NoFault;
192
193 // note this is a local, not BaseDynInst::fault
194 Fault trans_fault = cpu->translateDataReadReq(req);
195
196 if (trans_fault == NoFault && !(req->flags & UNCACHEABLE)) {
196 if (trans_fault == NoFault && !(req->isUncacheable())) {
197 // It's a valid address to cacheable space. Record key MemReq
198 // parameters so we can generate another one just like it for
199 // the timing access without calling translate() again (which
200 // might mess up the TLB).
201 effAddr = req->vaddr;
202 physEffAddr = req->paddr;
203 memReqFlags = req->flags;
204 } else {

--- 93 unchanged lines hidden --- 		197 // It's a valid address to cacheable space. Record key MemReq
198 // parameters so we can generate another one just like it for
199 // the timing access without calling translate() again (which
200 // might mess up the TLB).
201 effAddr = req->vaddr;
202 physEffAddr = req->paddr;
203 memReqFlags = req->flags;
204 } else {

--- 93 unchanged lines hidden ---