1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include <iostream>
32#include <set>
33#include <string>
34#include <sstream>
35
36#include "base/cprintf.hh"
37#include "base/trace.hh"
38#include "config/the_isa.hh"
39#include "cpu/base_dyn_inst.hh"
40#include "cpu/exetrace.hh"
41#include "mem/request.hh"
42#include "sim/faults.hh"
43
44#define NOHASH
45#ifndef NOHASH
46
47#include "base/hashmap.hh"
48
49unsigned int MyHashFunc(const BaseDynInst *addr)
50{
51 unsigned a = (unsigned)addr;
52 unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
53
54 return hash;
55}
56
57typedef m5::hash_map<const BaseDynInst *, const BaseDynInst *, MyHashFunc>
58my_hash_t;
59
60my_hash_t thishash;
61#endif
62
63template <class Impl>
64BaseDynInst<Impl>::BaseDynInst(StaticInstPtr _staticInst,
65 Addr inst_PC, Addr inst_NPC,
66 Addr inst_MicroPC,
67 Addr pred_PC, Addr pred_NPC,
68 Addr pred_MicroPC,
69 InstSeqNum seq_num, ImplCPU *cpu)
70 : staticInst(_staticInst), traceData(NULL), cpu(cpu)
71{
72 seqNum = seq_num;
73
74 bool nextIsMicro =
75 staticInst->isMicroop() && !staticInst->isLastMicroop();
76
77 PC = inst_PC;
78 microPC = inst_MicroPC;
79 if (nextIsMicro) {
80 nextPC = inst_PC;
81 nextNPC = inst_NPC;
82 nextMicroPC = microPC + 1;
83 } else {
84 nextPC = inst_NPC;
85 nextNPC = nextPC + sizeof(TheISA::MachInst);
86 nextMicroPC = 0;
87 }
88 predPC = pred_PC;
89 predNPC = pred_NPC;
90 predMicroPC = pred_MicroPC;
91 predTaken = false;
92
93 initVars();
94}
95
96template <class Impl>
97BaseDynInst<Impl>::BaseDynInst(TheISA::ExtMachInst inst,
98 Addr inst_PC, Addr inst_NPC,
99 Addr inst_MicroPC,
100 Addr pred_PC, Addr pred_NPC,
101 Addr pred_MicroPC,
102 InstSeqNum seq_num, ImplCPU *cpu)
103 : staticInst(inst, inst_PC), traceData(NULL), cpu(cpu)
104{
105 seqNum = seq_num;
106
107 bool nextIsMicro =
108 staticInst->isMicroop() && !staticInst->isLastMicroop();
109
110 PC = inst_PC;
111 microPC = inst_MicroPC;
112 if (nextIsMicro) {
113 nextPC = inst_PC;
114 nextNPC = inst_NPC;
115 nextMicroPC = microPC + 1;
116 } else {
117 nextPC = inst_NPC;
118 nextNPC = nextPC + sizeof(TheISA::MachInst);
119 nextMicroPC = 0;
120 }
121 predPC = pred_PC;
122 predNPC = pred_NPC;
123 predMicroPC = pred_MicroPC;
124 predTaken = false;
125
126 initVars();
127}
128
129template <class Impl>
130BaseDynInst<Impl>::BaseDynInst(StaticInstPtr &_staticInst)
131 : staticInst(_staticInst), traceData(NULL)
132{
133 seqNum = 0;
134 initVars();
135}
136
137template <class Impl>
138void
139BaseDynInst<Impl>::initVars()
140{
141 memData = NULL;
142 effAddr = 0;
143 effAddrValid = false;
144 physEffAddr = 0;
145
146 isUncacheable = false;
147 reqMade = false;
148 readyRegs = 0;
149
150 instResult.integer = 0;
151 recordResult = true;
152
153 status.reset();
154
155 eaCalcDone = false;
156 memOpDone = false;
|
158
159 lqIdx = -1;
160 sqIdx = -1;
161
162 // Eventually make this a parameter.
163 threadNumber = 0;
164
165 // Also make this a parameter, or perhaps get it from xc or cpu.
166 asid = 0;
167
168 // Initialize the fault to be NoFault.
169 fault = NoFault;
170
171#ifndef NDEBUG
172 ++cpu->instcount;
173
174 if (cpu->instcount > 1500) {
175#ifdef DEBUG
176 cpu->dumpInsts();
177 dumpSNList();
178#endif
179 assert(cpu->instcount <= 1500);
180 }
181
182 DPRINTF(DynInst,
183 "DynInst: [sn:%lli] Instruction created. Instcount for %s = %i\n",
184 seqNum, cpu->name(), cpu->instcount);
185#endif
186
187#ifdef DEBUG
188 cpu->snList.insert(seqNum);
189#endif
190}
191
192template <class Impl>
193BaseDynInst<Impl>::~BaseDynInst()
194{
195 if (memData) {
196 delete [] memData;
197 }
198
199 if (traceData) {
200 delete traceData;
201 }
202
203 fault = NoFault;
204
205#ifndef NDEBUG
206 --cpu->instcount;
207
208 DPRINTF(DynInst,
209 "DynInst: [sn:%lli] Instruction destroyed. Instcount for %s = %i\n",
210 seqNum, cpu->name(), cpu->instcount);
211#endif
212#ifdef DEBUG
213 cpu->snList.erase(seqNum);
214#endif
215}
216
217#ifdef DEBUG
218template <class Impl>
219void
220BaseDynInst<Impl>::dumpSNList()
221{
222 std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
223
224 int count = 0;
225 while (sn_it != cpu->snList.end()) {
226 cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
227 count++;
228 sn_it++;
229 }
230}
231#endif
232
233template <class Impl>
234void
235BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
236{
237 // This is the "functional" implementation of prefetch. Not much
238 // happens here since prefetches don't affect the architectural
239 // state.
240/*
241 // Generate a MemReq so we can translate the effective address.
242 MemReqPtr req = new MemReq(addr, thread->getXCProxy(), 1, flags);
243 req->asid = asid;
244
245 // Prefetches never cause faults.
246 fault = NoFault;
247
248 // note this is a local, not BaseDynInst::fault
249 Fault trans_fault = cpu->translateDataReadReq(req);
250
251 if (trans_fault == NoFault && !(req->isUncacheable())) {
252 // It's a valid address to cacheable space. Record key MemReq
253 // parameters so we can generate another one just like it for
254 // the timing access without calling translate() again (which
255 // might mess up the TLB).
256 effAddr = req->vaddr;
257 physEffAddr = req->paddr;
258 memReqFlags = req->flags;
259 } else {
260 // Bogus address (invalid or uncacheable space). Mark it by
261 // setting the eff_addr to InvalidAddr.
262 effAddr = physEffAddr = MemReq::inval_addr;
263 }
264
265 if (traceData) {
266 traceData->setAddr(addr);
267 }
268*/
269}
270
271template <class Impl>
272void
273BaseDynInst<Impl>::writeHint(Addr addr, int size, unsigned flags)
274{
275 // Not currently supported.
276}
277
278/**
279 * @todo Need to find a way to get the cache block size here.
280 */
281template <class Impl>
282Fault
283BaseDynInst<Impl>::copySrcTranslate(Addr src)
284{
285 // Not currently supported.
286 return NoFault;
287}
288
289/**
290 * @todo Need to find a way to get the cache block size here.
291 */
292template <class Impl>
293Fault
294BaseDynInst<Impl>::copy(Addr dest)
295{
296 // Not currently supported.
297 return NoFault;
298}
299
300template <class Impl>
301void
302BaseDynInst<Impl>::dump()
303{
304 cprintf("T%d : %#08d `", threadNumber, PC);
305 std::cout << staticInst->disassemble(PC);
306 cprintf("'\n");
307}
308
309template <class Impl>
310void
311BaseDynInst<Impl>::dump(std::string &outstring)
312{
313 std::ostringstream s;
314 s << "T" << threadNumber << " : 0x" << PC << " "
315 << staticInst->disassemble(PC);
316
317 outstring = s.str();
318}
319
320template <class Impl>
321void
322BaseDynInst<Impl>::markSrcRegReady()
323{
324 if (++readyRegs == numSrcRegs()) {
325 setCanIssue();
326 }
327}
328
329template <class Impl>
330void
331BaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx)
332{
333 _readySrcRegIdx[src_idx] = true;
334
335 markSrcRegReady();
336}
337
338template <class Impl>
339bool
340BaseDynInst<Impl>::eaSrcsReady()
341{
342 // For now I am assuming that src registers 1..n-1 are the ones that the
343 // EA calc depends on. (i.e. src reg 0 is the source of the data to be
344 // stored)
345
346 for (int i = 1; i < numSrcRegs(); ++i) {
347 if (!_readySrcRegIdx[i])
348 return false;
349 }
350
351 return true;
352}
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