1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 22 unchanged lines hidden (view full) --- 31#include <iostream> 32#include <set> 33#include <string> 34#include <sstream> 35 36#include "base/cprintf.hh" 37#include "base/trace.hh" 38 |
39#include "sim/faults.hh" |
40#include "cpu/exetrace.hh" 41#include "mem/request.hh" 42 43#include "cpu/base_dyn_inst.hh" 44 |
45#define NOHASH 46#ifndef NOHASH 47 48#include "base/hashmap.hh" 49 50unsigned int MyHashFunc(const BaseDynInst *addr) 51{ 52 unsigned a = (unsigned)addr; --- 4 unchanged lines hidden (view full) --- 57 58typedef m5::hash_map<const BaseDynInst *, const BaseDynInst *, MyHashFunc> 59my_hash_t; 60 61my_hash_t thishash; 62#endif 63 64template <class Impl> |
65BaseDynInst<Impl>::BaseDynInst(TheISA::ExtMachInst machInst, Addr inst_PC, |
66 Addr pred_PC, InstSeqNum seq_num, 67 ImplCPU *cpu) 68 : staticInst(machInst), traceData(NULL), cpu(cpu) 69{ 70 seqNum = seq_num; 71 72 PC = inst_PC; |
73 nextPC = PC + sizeof(TheISA::MachInst); 74 nextNPC = nextPC + sizeof(TheISA::MachInst); |
75 predPC = pred_PC; 76 77 initVars(); 78} 79 80template <class Impl> 81BaseDynInst<Impl>::BaseDynInst(StaticInstPtr &_staticInst) 82 : staticInst(_staticInst), traceData(NULL) --- 159 unchanged lines hidden (view full) --- 242 return NoFault; 243} 244 245template <class Impl> 246void 247BaseDynInst<Impl>::dump() 248{ 249 cprintf("T%d : %#08d `", threadNumber, PC); |
250 std::cout << staticInst->disassemble(PC); |
251 cprintf("'\n"); 252} 253 254template <class Impl> 255void 256BaseDynInst<Impl>::dump(std::string &outstring) 257{ 258 std::ostringstream s; --- 39 unchanged lines hidden --- |