1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 117 unchanged lines hidden (view full) --- 126 "DynInst: [sn:%lli] Instruction created. Instcount for %s = %i\n", 127 seqNum, cpu->name(), cpu->instcount); 128#endif 129 130#ifdef DEBUG 131 cpu->snList.insert(seqNum); 132#endif 133 |
134} 135 136template <class Impl> 137BaseDynInst<Impl>::~BaseDynInst() 138{ 139 if (memData) { 140 delete [] memData; 141 } --- 10 unchanged lines hidden (view full) --- 152 DPRINTF(DynInst, 153 "DynInst: [sn:%lli] Instruction destroyed. Instcount for %s = %i\n", 154 seqNum, cpu->name(), cpu->instcount); 155#endif 156#ifdef DEBUG 157 cpu->snList.erase(seqNum); 158#endif 159 |
160} 161 162#ifdef DEBUG 163template <class Impl> 164void 165BaseDynInst<Impl>::dumpSNList() 166{ 167 std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin(); --- 67 unchanged lines hidden --- |