1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include <iostream>
32#include <set>
33#include <string>
34#include <sstream>
35
36#include "base/cprintf.hh"
37#include "base/trace.hh"
38
39#include "sim/faults.hh"
40#include "cpu/exetrace.hh"
41#include "mem/request.hh"
42
43#include "cpu/base_dyn_inst.hh"
44
45#define NOHASH
46#ifndef NOHASH
47
48#include "base/hashmap.hh"
49
50unsigned int MyHashFunc(const BaseDynInst *addr)
51{
52 unsigned a = (unsigned)addr;
53 unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
54
55 return hash;
56}
57
58typedef m5::hash_map<const BaseDynInst *, const BaseDynInst *, MyHashFunc>
59my_hash_t;
60
61my_hash_t thishash;
62#endif
63
64template <class Impl>
65BaseDynInst<Impl>::BaseDynInst(TheISA::ExtMachInst machInst, Addr inst_PC,
66 Addr pred_PC, InstSeqNum seq_num,
67 ImplCPU *cpu)
68 : staticInst(machInst), traceData(NULL), cpu(cpu)
69{
70 seqNum = seq_num;
71
72 PC = inst_PC;
73 nextPC = PC + sizeof(TheISA::MachInst);
74 nextNPC = nextPC + sizeof(TheISA::MachInst);
75 predPC = pred_PC;
76
77 initVars();
78}
79
80template <class Impl>
81BaseDynInst<Impl>::BaseDynInst(StaticInstPtr &_staticInst)
82 : staticInst(_staticInst), traceData(NULL)
83{
84 seqNum = 0;
85 initVars();
86}
87
88template <class Impl>
89void
90BaseDynInst<Impl>::initVars()
91{
92 req = NULL;
93 memData = NULL;
94 effAddr = 0;
95 physEffAddr = 0;
96
97 readyRegs = 0;
98
99 instResult.integer = 0;
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include <iostream>
32#include <set>
33#include <string>
34#include <sstream>
35
36#include "base/cprintf.hh"
37#include "base/trace.hh"
38
39#include "sim/faults.hh"
40#include "cpu/exetrace.hh"
41#include "mem/request.hh"
42
43#include "cpu/base_dyn_inst.hh"
44
45#define NOHASH
46#ifndef NOHASH
47
48#include "base/hashmap.hh"
49
50unsigned int MyHashFunc(const BaseDynInst *addr)
51{
52 unsigned a = (unsigned)addr;
53 unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
54
55 return hash;
56}
57
58typedef m5::hash_map<const BaseDynInst *, const BaseDynInst *, MyHashFunc>
59my_hash_t;
60
61my_hash_t thishash;
62#endif
63
64template <class Impl>
65BaseDynInst<Impl>::BaseDynInst(TheISA::ExtMachInst machInst, Addr inst_PC,
66 Addr pred_PC, InstSeqNum seq_num,
67 ImplCPU *cpu)
68 : staticInst(machInst), traceData(NULL), cpu(cpu)
69{
70 seqNum = seq_num;
71
72 PC = inst_PC;
73 nextPC = PC + sizeof(TheISA::MachInst);
74 nextNPC = nextPC + sizeof(TheISA::MachInst);
75 predPC = pred_PC;
76
77 initVars();
78}
79
80template <class Impl>
81BaseDynInst<Impl>::BaseDynInst(StaticInstPtr &_staticInst)
82 : staticInst(_staticInst), traceData(NULL)
83{
84 seqNum = 0;
85 initVars();
86}
87
88template <class Impl>
89void
90BaseDynInst<Impl>::initVars()
91{
92 req = NULL;
93 memData = NULL;
94 effAddr = 0;
95 physEffAddr = 0;
96
97 readyRegs = 0;
98
99 instResult.integer = 0;
|
100
101 status.reset();
102
103 eaCalcDone = false;
104 memOpDone = false;
105
106 lqIdx = -1;
107 sqIdx = -1;
108
109 // Eventually make this a parameter.
110 threadNumber = 0;
111
112 // Also make this a parameter, or perhaps get it from xc or cpu.
113 asid = 0;
114
115 // Initialize the fault to be NoFault.
116 fault = NoFault;
117
118 ++instcount;
119
120 if (instcount > 1500) {
121 cpu->dumpInsts();
122#ifdef DEBUG
123 dumpSNList();
124#endif
125 assert(instcount <= 1500);
126 }
127
128 DPRINTF(DynInst, "DynInst: [sn:%lli] Instruction created. Instcount=%i\n",
129 seqNum, instcount);
130
131#ifdef DEBUG
132 cpu->snList.insert(seqNum);
133#endif
134}
135
136template <class Impl>
137BaseDynInst<Impl>::~BaseDynInst()
138{
139 if (req) {
140 delete req;
141 }
142
143 if (memData) {
144 delete [] memData;
145 }
146
147 if (traceData) {
148 delete traceData;
149 }
150
151 fault = NoFault;
152
153 --instcount;
154
155 DPRINTF(DynInst, "DynInst: [sn:%lli] Instruction destroyed. Instcount=%i\n",
156 seqNum, instcount);
157#ifdef DEBUG
158 cpu->snList.erase(seqNum);
159#endif
160}
161
162#ifdef DEBUG
163template <class Impl>
164void
165BaseDynInst<Impl>::dumpSNList()
166{
167 std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
168
169 int count = 0;
170 while (sn_it != cpu->snList.end()) {
171 cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
172 count++;
173 sn_it++;
174 }
175}
176#endif
177
178template <class Impl>
179void
180BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
181{
182 // This is the "functional" implementation of prefetch. Not much
183 // happens here since prefetches don't affect the architectural
184 // state.
185/*
186 // Generate a MemReq so we can translate the effective address.
187 MemReqPtr req = new MemReq(addr, thread->getXCProxy(), 1, flags);
188 req->asid = asid;
189
190 // Prefetches never cause faults.
191 fault = NoFault;
192
193 // note this is a local, not BaseDynInst::fault
194 Fault trans_fault = cpu->translateDataReadReq(req);
195
196 if (trans_fault == NoFault && !(req->isUncacheable())) {
197 // It's a valid address to cacheable space. Record key MemReq
198 // parameters so we can generate another one just like it for
199 // the timing access without calling translate() again (which
200 // might mess up the TLB).
201 effAddr = req->vaddr;
202 physEffAddr = req->paddr;
203 memReqFlags = req->flags;
204 } else {
205 // Bogus address (invalid or uncacheable space). Mark it by
206 // setting the eff_addr to InvalidAddr.
207 effAddr = physEffAddr = MemReq::inval_addr;
208 }
209
210 if (traceData) {
211 traceData->setAddr(addr);
212 }
213*/
214}
215
216template <class Impl>
217void
218BaseDynInst<Impl>::writeHint(Addr addr, int size, unsigned flags)
219{
220 // Not currently supported.
221}
222
223/**
224 * @todo Need to find a way to get the cache block size here.
225 */
226template <class Impl>
227Fault
228BaseDynInst<Impl>::copySrcTranslate(Addr src)
229{
230 // Not currently supported.
231 return NoFault;
232}
233
234/**
235 * @todo Need to find a way to get the cache block size here.
236 */
237template <class Impl>
238Fault
239BaseDynInst<Impl>::copy(Addr dest)
240{
241 // Not currently supported.
242 return NoFault;
243}
244
245template <class Impl>
246void
247BaseDynInst<Impl>::dump()
248{
249 cprintf("T%d : %#08d `", threadNumber, PC);
250 std::cout << staticInst->disassemble(PC);
251 cprintf("'\n");
252}
253
254template <class Impl>
255void
256BaseDynInst<Impl>::dump(std::string &outstring)
257{
258 std::ostringstream s;
259 s << "T" << threadNumber << " : 0x" << PC << " "
260 << staticInst->disassemble(PC);
261
262 outstring = s.str();
263}
264
265template <class Impl>
266void
267BaseDynInst<Impl>::markSrcRegReady()
268{
269 if (++readyRegs == numSrcRegs()) {
270 status.set(CanIssue);
271 }
272}
273
274template <class Impl>
275void
276BaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx)
277{
278 _readySrcRegIdx[src_idx] = true;
279
280 markSrcRegReady();
281}
282
283template <class Impl>
284bool
285BaseDynInst<Impl>::eaSrcsReady()
286{
287 // For now I am assuming that src registers 1..n-1 are the ones that the
288 // EA calc depends on. (i.e. src reg 0 is the source of the data to be
289 // stored)
290
291 for (int i = 1; i < numSrcRegs(); ++i) {
292 if (!_readySrcRegIdx[i])
293 return false;
294 }
295
296 return true;
297}
| 101
102 status.reset();
103
104 eaCalcDone = false;
105 memOpDone = false;
106
107 lqIdx = -1;
108 sqIdx = -1;
109
110 // Eventually make this a parameter.
111 threadNumber = 0;
112
113 // Also make this a parameter, or perhaps get it from xc or cpu.
114 asid = 0;
115
116 // Initialize the fault to be NoFault.
117 fault = NoFault;
118
119 ++instcount;
120
121 if (instcount > 1500) {
122 cpu->dumpInsts();
123#ifdef DEBUG
124 dumpSNList();
125#endif
126 assert(instcount <= 1500);
127 }
128
129 DPRINTF(DynInst, "DynInst: [sn:%lli] Instruction created. Instcount=%i\n",
130 seqNum, instcount);
131
132#ifdef DEBUG
133 cpu->snList.insert(seqNum);
134#endif
135}
136
137template <class Impl>
138BaseDynInst<Impl>::~BaseDynInst()
139{
140 if (req) {
141 delete req;
142 }
143
144 if (memData) {
145 delete [] memData;
146 }
147
148 if (traceData) {
149 delete traceData;
150 }
151
152 fault = NoFault;
153
154 --instcount;
155
156 DPRINTF(DynInst, "DynInst: [sn:%lli] Instruction destroyed. Instcount=%i\n",
157 seqNum, instcount);
158#ifdef DEBUG
159 cpu->snList.erase(seqNum);
160#endif
161}
162
163#ifdef DEBUG
164template <class Impl>
165void
166BaseDynInst<Impl>::dumpSNList()
167{
168 std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
169
170 int count = 0;
171 while (sn_it != cpu->snList.end()) {
172 cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
173 count++;
174 sn_it++;
175 }
176}
177#endif
178
179template <class Impl>
180void
181BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
182{
183 // This is the "functional" implementation of prefetch. Not much
184 // happens here since prefetches don't affect the architectural
185 // state.
186/*
187 // Generate a MemReq so we can translate the effective address.
188 MemReqPtr req = new MemReq(addr, thread->getXCProxy(), 1, flags);
189 req->asid = asid;
190
191 // Prefetches never cause faults.
192 fault = NoFault;
193
194 // note this is a local, not BaseDynInst::fault
195 Fault trans_fault = cpu->translateDataReadReq(req);
196
197 if (trans_fault == NoFault && !(req->isUncacheable())) {
198 // It's a valid address to cacheable space. Record key MemReq
199 // parameters so we can generate another one just like it for
200 // the timing access without calling translate() again (which
201 // might mess up the TLB).
202 effAddr = req->vaddr;
203 physEffAddr = req->paddr;
204 memReqFlags = req->flags;
205 } else {
206 // Bogus address (invalid or uncacheable space). Mark it by
207 // setting the eff_addr to InvalidAddr.
208 effAddr = physEffAddr = MemReq::inval_addr;
209 }
210
211 if (traceData) {
212 traceData->setAddr(addr);
213 }
214*/
215}
216
217template <class Impl>
218void
219BaseDynInst<Impl>::writeHint(Addr addr, int size, unsigned flags)
220{
221 // Not currently supported.
222}
223
224/**
225 * @todo Need to find a way to get the cache block size here.
226 */
227template <class Impl>
228Fault
229BaseDynInst<Impl>::copySrcTranslate(Addr src)
230{
231 // Not currently supported.
232 return NoFault;
233}
234
235/**
236 * @todo Need to find a way to get the cache block size here.
237 */
238template <class Impl>
239Fault
240BaseDynInst<Impl>::copy(Addr dest)
241{
242 // Not currently supported.
243 return NoFault;
244}
245
246template <class Impl>
247void
248BaseDynInst<Impl>::dump()
249{
250 cprintf("T%d : %#08d `", threadNumber, PC);
251 std::cout << staticInst->disassemble(PC);
252 cprintf("'\n");
253}
254
255template <class Impl>
256void
257BaseDynInst<Impl>::dump(std::string &outstring)
258{
259 std::ostringstream s;
260 s << "T" << threadNumber << " : 0x" << PC << " "
261 << staticInst->disassemble(PC);
262
263 outstring = s.str();
264}
265
266template <class Impl>
267void
268BaseDynInst<Impl>::markSrcRegReady()
269{
270 if (++readyRegs == numSrcRegs()) {
271 status.set(CanIssue);
272 }
273}
274
275template <class Impl>
276void
277BaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx)
278{
279 _readySrcRegIdx[src_idx] = true;
280
281 markSrcRegReady();
282}
283
284template <class Impl>
285bool
286BaseDynInst<Impl>::eaSrcsReady()
287{
288 // For now I am assuming that src registers 1..n-1 are the ones that the
289 // EA calc depends on. (i.e. src reg 0 is the source of the data to be
290 // stored)
291
292 for (int i = 1; i < numSrcRegs(); ++i) {
293 if (!_readySrcRegIdx[i])
294 return false;
295 }
296
297 return true;
298}
|