1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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71typedef m5::hash_map<const BaseDynInst *, const BaseDynInst *, MyHashFunc>
72my_hash_t;
73
74my_hash_t thishash;
75#endif
76
77template <class Impl>
78BaseDynInst<Impl>::BaseDynInst(StaticInstPtr _staticInst,
79 TheISA::PCState _pc, TheISA::PCState _predPC,
80 InstSeqNum seq_num, ImplCPU *cpu)
81 : staticInst(_staticInst), traceData(NULL), cpu(cpu)
82{
83 seqNum = seq_num;
84
85 pc = _pc;
86 predPC = _predPC;
87 predTaken = false;
88
89 initVars();
90}
91
92template <class Impl>
93BaseDynInst<Impl>::BaseDynInst(StaticInstPtr &_staticInst)
94 : staticInst(_staticInst), traceData(NULL)
95{
96 seqNum = 0;
97 initVars();
98}
99
100template <class Impl>
101void
102BaseDynInst<Impl>::initVars()

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