1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 117 unchanged lines hidden (view full) ---

126 "DynInst: [sn:%lli] Instruction created. Instcount for %s = %i\n",
127 seqNum, cpu->name(), cpu->instcount);
128#endif
129
130#ifdef DEBUG
131 cpu->snList.insert(seqNum);
132#endif
133
134 reqToVerify = NULL;
135}
136
137template <class Impl>
138BaseDynInst<Impl>::~BaseDynInst()
139{
140 if (memData) {
141 delete [] memData;
142 }

--- 10 unchanged lines hidden (view full) ---

153 DPRINTF(DynInst,
154 "DynInst: [sn:%lli] Instruction destroyed. Instcount for %s = %i\n",
155 seqNum, cpu->name(), cpu->instcount);
156#endif
157#ifdef DEBUG
158 cpu->snList.erase(seqNum);
159#endif
160
161 if (reqToVerify)
162 delete reqToVerify;
163}
164
165#ifdef DEBUG
166template <class Impl>
167void
168BaseDynInst<Impl>::dumpSNList()
169{
170 std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();

--- 67 unchanged lines hidden ---