1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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71typedef m5::hash_map<const BaseDynInst *, const BaseDynInst *, MyHashFunc>
72my_hash_t;
73
74my_hash_t thishash;
75#endif
76
77template <class Impl>
78BaseDynInst<Impl>::BaseDynInst(StaticInstPtr _staticInst,
79 StaticInstPtr _macroop,
80 TheISA::PCState _pc, TheISA::PCState _predPC,
81 InstSeqNum seq_num, ImplCPU *cpu)
82 : staticInst(_staticInst), macroop(_macroop), traceData(NULL), cpu(cpu)
83{
84 seqNum = seq_num;
85
86 pc = _pc;
87 predPC = _predPC;
88 predTaken = false;
89
90 initVars();
91}
92
93template <class Impl>
94BaseDynInst<Impl>::BaseDynInst(StaticInstPtr _staticInst,
95 StaticInstPtr _macroop)
96 : staticInst(_staticInst), macroop(_macroop), traceData(NULL)
97{
98 seqNum = 0;
99 initVars();
100}
101
102template <class Impl>
103void
104BaseDynInst<Impl>::initVars()

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