1/*
2 * Copyright (c) 2011-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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246 public:
247
248 // Mask to align PCs to MachInst sized boundaries
249 static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
250
251 /// Provide access to the tracer pointer
252 Trace::InstTracer * getTracer() { return tracer; }
253
254 /// Notify the CPU that the indicated context is now active. The
255 /// delay parameter indicates the number of ticks to wait before
256 /// executing (typically 0 or 1).
257 virtual void activateContext(ThreadID thread_num, Cycles delay) {}
254 /// Notify the CPU that the indicated context is now active.
255 virtual void activateContext(ThreadID thread_num) {}
256
257 /// Notify the CPU that the indicated context is now suspended.
258 virtual void suspendContext(ThreadID thread_num) {}
259
260 /// Notify the CPU that the indicated context is now deallocated.
261 virtual void deallocateContext(ThreadID thread_num) {}
262
263 /// Notify the CPU that the indicated context is now halted.

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278 { return reinterpret_cast<const Params *>(_params); }
279 BaseCPU(Params *params, bool is_checker = false);
280 virtual ~BaseCPU();
281
282 virtual void init();
283 virtual void startup();
284 virtual void regStats();
285
288 virtual void activateWhenReady(ThreadID tid) {};
289
286 void registerThreadContexts();
287
288 /**
289 * Prepare for another CPU to take over execution.
290 *
291 * When this method exits, all internal state should have been
292 * flushed. After the method returns, the simulator calls
293 * takeOverFrom() on the new CPU with this CPU as its parameter.

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