base.cc (9523:b8c8437f71d9) base.cc (9608:e2b6b86fda03)
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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307}
308
309BaseMasterPort &
310BaseCPU::getMasterPort(const string &if_name, PortID idx)
311{
312 // Get the right port based on name. This applies to all the
313 // subclasses of the base CPU and relies on their implementation
314 // of getDataPort and getInstPort. In all cases there methods
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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307}
308
309BaseMasterPort &
310BaseCPU::getMasterPort(const string &if_name, PortID idx)
311{
312 // Get the right port based on name. This applies to all the
313 // subclasses of the base CPU and relies on their implementation
314 // of getDataPort and getInstPort. In all cases there methods
315 // return a CpuPort pointer.
315 // return a MasterPort pointer.
316 if (if_name == "dcache_port")
317 return getDataPort();
318 else if (if_name == "icache_port")
319 return getInstPort();
320 else
321 return MemObject::getMasterPort(if_name, idx);
322}
323

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580 currentFunctionEnd = pc + 1;
581 }
582
583 ccprintf(*functionTraceStream, " (%d)\n%d: %s",
584 curTick() - functionEntryTick, curTick(), sym_str);
585 functionEntryTick = curTick();
586 }
587}
316 if (if_name == "dcache_port")
317 return getDataPort();
318 else if (if_name == "icache_port")
319 return getInstPort();
320 else
321 return MemObject::getMasterPort(if_name, idx);
322}
323

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580 currentFunctionEnd = pc + 1;
581 }
582
583 ccprintf(*functionTraceStream, " (%d)\n%d: %s",
584 curTick() - functionEntryTick, curTick(), sym_str);
585 functionEntryTick = curTick();
586 }
587}
588
589bool
590BaseCPU::CpuPort::recvTimingResp(PacketPtr pkt)
591{
592 panic("BaseCPU doesn't expect recvTiming!\n");
593 return true;
594}
595
596void
597BaseCPU::CpuPort::recvRetry()
598{
599 panic("BaseCPU doesn't expect recvRetry!\n");
600}
601
602void
603BaseCPU::CpuPort::recvFunctionalSnoop(PacketPtr pkt)
604{
605 // No internal storage to update (in the general case). A CPU with
606 // internal storage, e.g. an LSQ that should be part of the
607 // coherent memory has to check against stored data.
608}