base.cc (9152:86c0e6ca5e7c) base.cc (9157:e0bad9d7bbd6)
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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110
111const char *
112CPUProgressEvent::description() const
113{
114 return "CPU Progress";
115}
116
117BaseCPU::BaseCPU(Params *p, bool is_checker)
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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110
111const char *
112CPUProgressEvent::description() const
113{
114 return "CPU Progress";
115}
116
117BaseCPU::BaseCPU(Params *p, bool is_checker)
118 : MemObject(p), clock(p->clock), instCnt(0), _cpuId(p->cpu_id),
118 : MemObject(p), instCnt(0), _cpuId(p->cpu_id),
119 _instMasterId(p->system->getMasterId(name() + ".inst")),
120 _dataMasterId(p->system->getMasterId(name() + ".data")),
121 interrupts(p->interrupts),
119 _instMasterId(p->system->getMasterId(name() + ".inst")),
120 _dataMasterId(p->system->getMasterId(name() + ".data")),
121 interrupts(p->interrupts),
122 numThreads(p->numThreads), system(p->system),
123 phase(p->phase)
122 numThreads(p->numThreads), system(p->system)
124{
123{
125// currentTick = curTick();
126
127 // if Python did not provide a valid ID, do it here
128 if (_cpuId == -1 ) {
129 _cpuId = cpuList.size();
130 }
131
132 // add self to global list of CPUs
133 cpuList.push_back(this);
134

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312 if (if_name == "dcache_port")
313 return getDataPort();
314 else if (if_name == "icache_port")
315 return getInstPort();
316 else
317 return MemObject::getMasterPort(if_name, idx);
318}
319
124 // if Python did not provide a valid ID, do it here
125 if (_cpuId == -1 ) {
126 _cpuId = cpuList.size();
127 }
128
129 // add self to global list of CPUs
130 cpuList.push_back(this);
131

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309 if (if_name == "dcache_port")
310 return getDataPort();
311 else if (if_name == "icache_port")
312 return getInstPort();
313 else
314 return MemObject::getMasterPort(if_name, idx);
315}
316
320Tick
321BaseCPU::nextCycle()
322{
323 Tick next_tick = curTick() - phase + clock - 1;
324 next_tick -= (next_tick % clock);
325 next_tick += phase;
326 return next_tick;
327}
328
329Tick
330BaseCPU::nextCycle(Tick begin_tick)
331{
332 Tick next_tick = begin_tick;
333 if (next_tick % clock != 0)
334 next_tick = next_tick - (next_tick % clock) + clock;
335 next_tick += phase;
336
337 assert(next_tick >= curTick());
338 return next_tick;
339}
340
341void
342BaseCPU::registerThreadContexts()
343{
344 ThreadID size = threadContexts.size();
345 for (ThreadID tid = 0; tid < size; ++tid) {
346 ThreadContext *tc = threadContexts[tid];
347
348 /** This is so that contextId and cpuId match where there is a

--- 214 unchanged lines hidden --- 		317void
318BaseCPU::registerThreadContexts()
319{
320 ThreadID size = threadContexts.size();
321 for (ThreadID tid = 0; tid < size; ++tid) {
322 ThreadContext *tc = threadContexts[tid];
323
324 /** This is so that contextId and cpuId match where there is a

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