base.cc (8876:44f8e7bb7fdf) base.cc (8887:20ea02da9c53)
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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48#include <string>
49
50#include "arch/tlb.hh"
51#include "base/loader/symtab.hh"
52#include "base/cprintf.hh"
53#include "base/misc.hh"
54#include "base/output.hh"
55#include "base/trace.hh"
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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48#include <string>
49
50#include "arch/tlb.hh"
51#include "base/loader/symtab.hh"
52#include "base/cprintf.hh"
53#include "base/misc.hh"
54#include "base/output.hh"
55#include "base/trace.hh"
56#include "config/use_checker.hh"
57#include "cpu/base.hh"
56#include "cpu/base.hh"
57#include "cpu/checker/cpu.hh"
58#include "cpu/cpuevent.hh"
59#include "cpu/profile.hh"
60#include "cpu/thread_context.hh"
61#include "debug/SyscallVerbose.hh"
62#include "params/BaseCPU.hh"
63#include "sim/full_system.hh"
64#include "sim/process.hh"
65#include "sim/sim_events.hh"
66#include "sim/sim_exit.hh"
67#include "sim/system.hh"
68
58#include "cpu/cpuevent.hh"
59#include "cpu/profile.hh"
60#include "cpu/thread_context.hh"
61#include "debug/SyscallVerbose.hh"
62#include "params/BaseCPU.hh"
63#include "sim/full_system.hh"
64#include "sim/process.hh"
65#include "sim/sim_events.hh"
66#include "sim/sim_exit.hh"
67#include "sim/system.hh"
68
69#if USE_CHECKER
70#include "cpu/checker/cpu.hh"
71#endif
72
73// Hack
74#include "sim/stat_control.hh"
75
76using namespace std;
77
78vector<BaseCPU *> BaseCPU::cpuList;
79
80// This variable reflects the max number of threads in any CPU. Be

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426 }
427 if (new_dtb_port && !new_dtb_port->isConnected()) {
428 assert(old_dtb_port);
429 Port *peer = old_dtb_port->getPeer();;
430 new_dtb_port->setPeer(peer);
431 peer->setPeer(new_dtb_port);
432 }
433
69// Hack
70#include "sim/stat_control.hh"
71
72using namespace std;
73
74vector<BaseCPU *> BaseCPU::cpuList;
75
76// This variable reflects the max number of threads in any CPU. Be

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422 }
423 if (new_dtb_port && !new_dtb_port->isConnected()) {
424 assert(old_dtb_port);
425 Port *peer = old_dtb_port->getPeer();;
426 new_dtb_port->setPeer(peer);
427 peer->setPeer(new_dtb_port);
428 }
429
434#if USE_CHECKER
435 Port *old_checker_itb_port, *old_checker_dtb_port;
436 Port *new_checker_itb_port, *new_checker_dtb_port;
430 // Checker whether or not we have to transfer CheckerCPU
431 // objects over in the switch
432 CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr();
433 CheckerCPU *newChecker = newTC->getCheckerCpuPtr();
434 if (oldChecker && newChecker) {
435 Port *old_checker_itb_port, *old_checker_dtb_port;
436 Port *new_checker_itb_port, *new_checker_dtb_port;
437
437
438 CheckerCPU *oldChecker =
439 dynamic_cast<CheckerCPU*>(oldTC->getCheckerCpuPtr());
440 CheckerCPU *newChecker =
441 dynamic_cast<CheckerCPU*>(newTC->getCheckerCpuPtr());
442 old_checker_itb_port = oldChecker->getITBPtr()->getPort();
443 old_checker_dtb_port = oldChecker->getDTBPtr()->getPort();
444 new_checker_itb_port = newChecker->getITBPtr()->getPort();
445 new_checker_dtb_port = newChecker->getDTBPtr()->getPort();
438 old_checker_itb_port = oldChecker->getITBPtr()->getPort();
439 old_checker_dtb_port = oldChecker->getDTBPtr()->getPort();
440 new_checker_itb_port = newChecker->getITBPtr()->getPort();
441 new_checker_dtb_port = newChecker->getDTBPtr()->getPort();
446
442
447 // Move over any table walker ports if they exist for checker
448 if (new_checker_itb_port && !new_checker_itb_port->isConnected()) {
449 assert(old_checker_itb_port);
450 Port *peer = old_checker_itb_port->getPeer();;
451 new_checker_itb_port->setPeer(peer);
452 peer->setPeer(new_checker_itb_port);
443 // Move over any table walker ports if they exist for checker
444 if (new_checker_itb_port && !new_checker_itb_port->isConnected()) {
445 assert(old_checker_itb_port);
446 Port *peer = old_checker_itb_port->getPeer();;
447 new_checker_itb_port->setPeer(peer);
448 peer->setPeer(new_checker_itb_port);
449 }
450 if (new_checker_dtb_port && !new_checker_dtb_port->isConnected()) {
451 assert(old_checker_dtb_port);
452 Port *peer = old_checker_dtb_port->getPeer();;
453 new_checker_dtb_port->setPeer(peer);
454 peer->setPeer(new_checker_dtb_port);
455 }
453 }
456 }
454 if (new_checker_dtb_port && !new_checker_dtb_port->isConnected()) {
455 assert(old_checker_dtb_port);
456 Port *peer = old_checker_dtb_port->getPeer();;
457 new_checker_dtb_port->setPeer(peer);
458 peer->setPeer(new_checker_dtb_port);
459 }
460#endif
461
462 }
463
464 interrupts = oldCPU->interrupts;
465 interrupts->setCPU(this);
466
467 if (FullSystem) {
468 for (ThreadID i = 0; i < size; ++i)
469 threadContexts[i]->profileClear();

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458
459 interrupts = oldCPU->interrupts;
460 interrupts->setCPU(this);
461
462 if (FullSystem) {
463 for (ThreadID i = 0; i < size; ++i)
464 threadContexts[i]->profileClear();

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