base.cc (8834:21e8d54ecf07) base.cc (8850:ed91b534ed04)
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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291 stringstream namestr;
292 ccprintf(namestr, "%s.ctx%d", name(), i);
293 threadContexts[i]->regStats(namestr.str());
294 }
295 } else if (size == 1)
296 threadContexts[0]->regStats(name());
297}
298
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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291 stringstream namestr;
292 ccprintf(namestr, "%s.ctx%d", name(), i);
293 threadContexts[i]->regStats(namestr.str());
294 }
295 } else if (size == 1)
296 threadContexts[0]->regStats(name());
297}
298
299Port *
300BaseCPU::getPort(const string &if_name, int idx)
301{
302 // Get the right port based on name. This applies to all the
303 // subclasses of the base CPU and relies on their implementation
304 // of getDataPort and getInstPort. In all cases there methods
305 // return a CpuPort pointer.
306 if (if_name == "dcache_port")
307 return &getDataPort();
308 else if (if_name == "icache_port")
309 return &getInstPort();
310 else
311 panic("CPU %s has no port named %s\n", name(), if_name);
312}
313
299Tick
300BaseCPU::nextCycle()
301{
302 Tick next_tick = curTick() - phase + clock - 1;
303 next_tick -= (next_tick % clock);
304 next_tick += phase;
305 return next_tick;
306}

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358{
359 if (profileEvent && profileEvent->scheduled())
360 deschedule(profileEvent);
361}
362
363void
364BaseCPU::takeOverFrom(BaseCPU *oldCPU)
365{
314Tick
315BaseCPU::nextCycle()
316{
317 Tick next_tick = curTick() - phase + clock - 1;
318 next_tick -= (next_tick % clock);
319 next_tick += phase;
320 return next_tick;
321}

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373{
374 if (profileEvent && profileEvent->scheduled())
375 deschedule(profileEvent);
376}
377
378void
379BaseCPU::takeOverFrom(BaseCPU *oldCPU)
380{
366 Port *ic = getPort("icache_port");
367 Port *dc = getPort("dcache_port");
381 CpuPort &ic = getInstPort();
382 CpuPort &dc = getDataPort();
368 assert(threadContexts.size() == oldCPU->threadContexts.size());
369
370 _cpuId = oldCPU->cpuId();
371
372 ThreadID size = threadContexts.size();
373 for (ThreadID i = 0; i < size; ++i) {
374 ThreadContext *newTC = threadContexts[i];
375 ThreadContext *oldTC = oldCPU->threadContexts[i];

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448
449 if (profileEvent)
450 schedule(profileEvent, curTick());
451 }
452
453 // Connect new CPU to old CPU's memory only if new CPU isn't
454 // connected to anything. Also connect old CPU's memory to new
455 // CPU.
383 assert(threadContexts.size() == oldCPU->threadContexts.size());
384
385 _cpuId = oldCPU->cpuId();
386
387 ThreadID size = threadContexts.size();
388 for (ThreadID i = 0; i < size; ++i) {
389 ThreadContext *newTC = threadContexts[i];
390 ThreadContext *oldTC = oldCPU->threadContexts[i];

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463
464 if (profileEvent)
465 schedule(profileEvent, curTick());
466 }
467
468 // Connect new CPU to old CPU's memory only if new CPU isn't
469 // connected to anything. Also connect old CPU's memory to new
470 // CPU.
456 if (!ic->isConnected()) {
457 Port *peer = oldCPU->getPort("icache_port")->getPeer();
458 ic->setPeer(peer);
459 peer->setPeer(ic);
471 if (!ic.isConnected()) {
472 Port *peer = oldCPU->getInstPort().getPeer();
473 ic.setPeer(peer);
474 peer->setPeer(&ic);
460 }
461
475 }
476
462 if (!dc->isConnected()) {
463 Port *peer = oldCPU->getPort("dcache_port")->getPeer();
464 dc->setPeer(peer);
465 peer->setPeer(dc);
477 if (!dc.isConnected()) {
478 Port *peer = oldCPU->getDataPort().getPeer();
479 dc.setPeer(peer);
480 peer->setPeer(&dc);
466 }
467}
468
469
470BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval)
471 : cpu(_cpu), interval(_interval)
472{ }
473

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482}
483
484
485BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval)
486 : cpu(_cpu), interval(_interval)
487{ }
488

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