base.cc (13818:f0126488ef9e) base.cc (13892:0182a0601f66)
1/*
2 * Copyright (c) 2011-2012,2016-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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121
122const char *
123CPUProgressEvent::description() const
124{
125 return "CPU Progress";
126}
127
128BaseCPU::BaseCPU(Params *p, bool is_checker)
1/*
2 * Copyright (c) 2011-2012,2016-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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121
122const char *
123CPUProgressEvent::description() const
124{
125 return "CPU Progress";
126}
127
128BaseCPU::BaseCPU(Params *p, bool is_checker)
129 : MemObject(p), instCnt(0), _cpuId(p->cpu_id), _socketId(p->socket_id),
129 : ClockedObject(p), instCnt(0), _cpuId(p->cpu_id), _socketId(p->socket_id),
130 _instMasterId(p->system->getMasterId(this, "inst")),
131 _dataMasterId(p->system->getMasterId(this, "data")),
132 _taskId(ContextSwitchTaskId::Unknown), _pid(invldPid),
133 _switchedOut(p->switched_out), _cacheLineSize(p->system->cacheLineSize()),
134 interrupts(p->interrupts), profileEvent(NULL),
135 numThreads(p->numThreads), system(p->system),
136 previousCycle(0), previousState(CPU_STATE_SLEEP),
137 functionTraceStream(nullptr), currentFunctionStart(0),

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416
417 if (inst->isControl())
418 ppRetiredBranches->notify(1);
419}
420
421void
422BaseCPU::regStats()
423{
130 _instMasterId(p->system->getMasterId(this, "inst")),
131 _dataMasterId(p->system->getMasterId(this, "data")),
132 _taskId(ContextSwitchTaskId::Unknown), _pid(invldPid),
133 _switchedOut(p->switched_out), _cacheLineSize(p->system->cacheLineSize()),
134 interrupts(p->interrupts), profileEvent(NULL),
135 numThreads(p->numThreads), system(p->system),
136 previousCycle(0), previousState(CPU_STATE_SLEEP),
137 functionTraceStream(nullptr), currentFunctionStart(0),

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416
417 if (inst->isControl())
418 ppRetiredBranches->notify(1);
419}
420
421void
422BaseCPU::regStats()
423{
424 MemObject::regStats();
424 ClockedObject::regStats();
425
426 using namespace Stats;
427
428 numCycles
429 .name(name() + ".numCycles")
430 .desc("number of cpu cycles simulated")
431 ;
432

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457 // Get the right port based on name. This applies to all the
458 // subclasses of the base CPU and relies on their implementation
459 // of getDataPort and getInstPort.
460 if (if_name == "dcache_port")
461 return getDataPort();
462 else if (if_name == "icache_port")
463 return getInstPort();
464 else
425
426 using namespace Stats;
427
428 numCycles
429 .name(name() + ".numCycles")
430 .desc("number of cpu cycles simulated")
431 ;
432

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457 // Get the right port based on name. This applies to all the
458 // subclasses of the base CPU and relies on their implementation
459 // of getDataPort and getInstPort.
460 if (if_name == "dcache_port")
461 return getDataPort();
462 else if (if_name == "icache_port")
463 return getInstPort();
464 else
465 return MemObject::getPort(if_name, idx);
465 return ClockedObject::getPort(if_name, idx);
466}
467
468void
469BaseCPU::registerThreadContexts()
470{
471 assert(system->multiThread || numThreads == 1);
472
473 ThreadID size = threadContexts.size();

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467
468void
469BaseCPU::registerThreadContexts()
470{
471 assert(system->multiThread || numThreads == 1);
472
473 ThreadID size = threadContexts.size();

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