| base.cc (12680:91f4d6668b4f) | base.cc (12749:223c83ed9979) |
|---|---|
| 1/* 2 * Copyright (c) 2011-2012,2016-2017 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 304 unchanged lines hidden (view full) --- 313} 314 315void 316BaseCPU::mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseTLB *dtb) 317{ 318 assert(tid < numThreads); 319 AddressMonitor &monitor = addressMonitor[tid]; 320 | 1/* 2 * Copyright (c) 2011-2012,2016-2017 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 304 unchanged lines hidden (view full) --- 313} 314 315void 316BaseCPU::mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseTLB *dtb) 317{ 318 assert(tid < numThreads); 319 AddressMonitor &monitor = addressMonitor[tid]; 320 |
| 321 Request req; | 321 RequestPtr req; |
| 322 Addr addr = monitor.vAddr; 323 int block_size = cacheLineSize(); 324 uint64_t mask = ~((uint64_t)(block_size - 1)); 325 int size = block_size; 326 327 //The address of the next line if it crosses a cache line boundary. 328 Addr secondAddr = roundDown(addr + size - 1, block_size); 329 330 if (secondAddr > addr) 331 size = secondAddr - addr; 332 | 322 Addr addr = monitor.vAddr; 323 int block_size = cacheLineSize(); 324 uint64_t mask = ~((uint64_t)(block_size - 1)); 325 int size = block_size; 326 327 //The address of the next line if it crosses a cache line boundary. 328 Addr secondAddr = roundDown(addr + size - 1, block_size); 329 330 if (secondAddr > addr) 331 size = secondAddr - addr; 332 |
| 333 req.setVirt(0, addr, size, 0x0, dataMasterId(), tc->instAddr()); | 333 req->setVirt(0, addr, size, 0x0, dataMasterId(), tc->instAddr()); |
| 334 335 // translate to physical address | 334 335 // translate to physical address |
| 336 Fault fault = dtb->translateAtomic(&req, tc, BaseTLB::Read); | 336 Fault fault = dtb->translateAtomic(req, tc, BaseTLB::Read); |
| 337 assert(fault == NoFault); 338 | 337 assert(fault == NoFault); 338 |
| 339 monitor.pAddr = req.getPaddr() & mask; | 339 monitor.pAddr = req->getPaddr() & mask; |
| 340 monitor.waiting = true; 341 342 DPRINTF(Mwait,"[tid:%d] mwait called (vAddr=0x%lx, line's paddr=0x%lx)\n", 343 tid, monitor.vAddr, monitor.pAddr); 344} 345 346void 347BaseCPU::init() --- 511 unchanged lines hidden --- | 340 monitor.waiting = true; 341 342 DPRINTF(Mwait,"[tid:%d] mwait called (vAddr=0x%lx, line's paddr=0x%lx)\n", 343 tid, monitor.vAddr, monitor.pAddr); 344} 345 346void 347BaseCPU::init() --- 511 unchanged lines hidden --- |