base.cc (12277:e6455b421c4b) base.cc (12284:b91c036913da)
1/*
2 * Copyright (c) 2011-2012,2016-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 119 unchanged lines hidden (view full) ---

128BaseCPU::BaseCPU(Params *p, bool is_checker)
129 : MemObject(p), instCnt(0), _cpuId(p->cpu_id), _socketId(p->socket_id),
130 _instMasterId(p->system->getMasterId(name() + ".inst")),
131 _dataMasterId(p->system->getMasterId(name() + ".data")),
132 _taskId(ContextSwitchTaskId::Unknown), _pid(invldPid),
133 _switchedOut(p->switched_out), _cacheLineSize(p->system->cacheLineSize()),
134 interrupts(p->interrupts), profileEvent(NULL),
135 numThreads(p->numThreads), system(p->system),
1/*
2 * Copyright (c) 2011-2012,2016-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 119 unchanged lines hidden (view full) ---

128BaseCPU::BaseCPU(Params *p, bool is_checker)
129 : MemObject(p), instCnt(0), _cpuId(p->cpu_id), _socketId(p->socket_id),
130 _instMasterId(p->system->getMasterId(name() + ".inst")),
131 _dataMasterId(p->system->getMasterId(name() + ".data")),
132 _taskId(ContextSwitchTaskId::Unknown), _pid(invldPid),
133 _switchedOut(p->switched_out), _cacheLineSize(p->system->cacheLineSize()),
134 interrupts(p->interrupts), profileEvent(NULL),
135 numThreads(p->numThreads), system(p->system),
136 previousCycle(0), previousState(CPU_STATE_SLEEP),
136 functionTraceStream(nullptr), currentFunctionStart(0),
137 currentFunctionEnd(0), functionEntryTick(0),
138 addressMonitor(p->numThreads),
139 syscallRetryLatency(p->syscallRetryLatency),
140 pwrGatingLatency(p->pwr_gating_latency),
141 powerGatingOnIdle(p->power_gating_on_idle),
142 enterPwrGatingEvent([this]{ enterPwrGating(); }, name())
143{

--- 236 unchanged lines hidden (view full) ---

380 ptr.reset(new ProbePoints::PMU(getProbeManager(), name));
381
382 return ptr;
383}
384
385void
386BaseCPU::regProbePoints()
387{
137 functionTraceStream(nullptr), currentFunctionStart(0),
138 currentFunctionEnd(0), functionEntryTick(0),
139 addressMonitor(p->numThreads),
140 syscallRetryLatency(p->syscallRetryLatency),
141 pwrGatingLatency(p->pwr_gating_latency),
142 powerGatingOnIdle(p->power_gating_on_idle),
143 enterPwrGatingEvent([this]{ enterPwrGating(); }, name())
144{

--- 236 unchanged lines hidden (view full) ---

381 ptr.reset(new ProbePoints::PMU(getProbeManager(), name));
382
383 return ptr;
384}
385
386void
387BaseCPU::regProbePoints()
388{
388 ppCycles = pmuProbePoint("Cycles");
389 ppAllCycles = pmuProbePoint("Cycles");
390 ppActiveCycles = pmuProbePoint("ActiveCycles");
389
390 ppRetiredInsts = pmuProbePoint("RetiredInsts");
391 ppRetiredLoads = pmuProbePoint("RetiredLoads");
392 ppRetiredStores = pmuProbePoint("RetiredStores");
393 ppRetiredBranches = pmuProbePoint("RetiredBranches");
391
392 ppRetiredInsts = pmuProbePoint("RetiredInsts");
393 ppRetiredLoads = pmuProbePoint("RetiredLoads");
394 ppRetiredStores = pmuProbePoint("RetiredStores");
395 ppRetiredBranches = pmuProbePoint("RetiredBranches");
396
397 ppSleeping = new ProbePointArg<bool>(this->getProbeManager(),
398 "Sleeping");
394}
395
396void
397BaseCPU::probeInstCommit(const StaticInstPtr &inst)
398{
399 if (!inst->isMicroop() || inst->isLastMicroop())
400 ppRetiredInsts->notify(1);
401

--- 113 unchanged lines hidden (view full) ---

515}
516
517void
518BaseCPU::activateContext(ThreadID thread_num)
519{
520 // Squash enter power gating event while cpu gets activated
521 if (enterPwrGatingEvent.scheduled())
522 deschedule(enterPwrGatingEvent);
399}
400
401void
402BaseCPU::probeInstCommit(const StaticInstPtr &inst)
403{
404 if (!inst->isMicroop() || inst->isLastMicroop())
405 ppRetiredInsts->notify(1);
406

--- 113 unchanged lines hidden (view full) ---

520}
521
522void
523BaseCPU::activateContext(ThreadID thread_num)
524{
525 // Squash enter power gating event while cpu gets activated
526 if (enterPwrGatingEvent.scheduled())
527 deschedule(enterPwrGatingEvent);
523
524 // For any active thread running, update CPU power state to active (ON)
525 ClockedObject::pwrState(Enums::PwrState::ON);
528 // For any active thread running, update CPU power state to active (ON)
529 ClockedObject::pwrState(Enums::PwrState::ON);
530
531 updateCycleCounters(CPU_STATE_WAKEUP);
526}
527
528void
529BaseCPU::suspendContext(ThreadID thread_num)
530{
531 // Check if all threads are suspended
532 for (auto t : threadContexts) {
533 if (t->status() != ThreadContext::Suspended) {
534 return;
535 }
536 }
537
532}
533
534void
535BaseCPU::suspendContext(ThreadID thread_num)
536{
537 // Check if all threads are suspended
538 for (auto t : threadContexts) {
539 if (t->status() != ThreadContext::Suspended) {
540 return;
541 }
542 }
543
544 // All CPU thread are suspended, update cycle count
545 updateCycleCounters(CPU_STATE_SLEEP);
546
538 // All CPU threads suspended, enter lower power state for the CPU
539 ClockedObject::pwrState(Enums::PwrState::CLK_GATED);
540
541 // If pwrGatingLatency is set to 0 then this mechanism is disabled
542 if (powerGatingOnIdle) {
543 // Schedule power gating event when clock gated for pwrGatingLatency
544 // cycles
545 schedule(enterPwrGatingEvent, clockEdge(pwrGatingLatency));
546 }
547}
548
549void
547 // All CPU threads suspended, enter lower power state for the CPU
548 ClockedObject::pwrState(Enums::PwrState::CLK_GATED);
549
550 // If pwrGatingLatency is set to 0 then this mechanism is disabled
551 if (powerGatingOnIdle) {
552 // Schedule power gating event when clock gated for pwrGatingLatency
553 // cycles
554 schedule(enterPwrGatingEvent, clockEdge(pwrGatingLatency));
555 }
556}
557
558void
559BaseCPU::haltContext(ThreadID thread_num)
560{
561 updateCycleCounters(BaseCPU::CPU_STATE_SLEEP);
562}
563
564void
550BaseCPU::enterPwrGating(void)
551{
552 ClockedObject::pwrState(Enums::PwrState::OFF);
553}
554
555void
556BaseCPU::switchOut()
557{

--- 16 unchanged lines hidden (view full) ---

574 assert(threadContexts.size() == oldCPU->threadContexts.size());
575 assert(_cpuId == oldCPU->cpuId());
576 assert(_switchedOut);
577 assert(oldCPU != this);
578 _pid = oldCPU->getPid();
579 _taskId = oldCPU->taskId();
580 // Take over the power state of the switchedOut CPU
581 ClockedObject::pwrState(oldCPU->pwrState());
565BaseCPU::enterPwrGating(void)
566{
567 ClockedObject::pwrState(Enums::PwrState::OFF);
568}
569
570void
571BaseCPU::switchOut()
572{

--- 16 unchanged lines hidden (view full) ---

589 assert(threadContexts.size() == oldCPU->threadContexts.size());
590 assert(_cpuId == oldCPU->cpuId());
591 assert(_switchedOut);
592 assert(oldCPU != this);
593 _pid = oldCPU->getPid();
594 _taskId = oldCPU->taskId();
595 // Take over the power state of the switchedOut CPU
596 ClockedObject::pwrState(oldCPU->pwrState());
597
598 previousState = oldCPU->previousState;
599 previousCycle = oldCPU->previousCycle;
600
582 _switchedOut = false;
583
584 ThreadID size = threadContexts.size();
585 for (ThreadID i = 0; i < size; ++i) {
586 ThreadContext *newTC = threadContexts[i];
587 ThreadContext *oldTC = oldCPU->threadContexts[i];
588
589 newTC->takeOverFrom(oldTC);

--- 250 unchanged lines hidden --- 		601 _switchedOut = false;
602
603 ThreadID size = threadContexts.size();
604 for (ThreadID i = 0; i < size; ++i) {
605 ThreadContext *newTC = threadContexts[i];
606 ThreadContext *oldTC = oldCPU->threadContexts[i];
607
608 newTC->takeOverFrom(oldTC);

--- 250 unchanged lines hidden ---