base.cc (10464:2a0fe8bca031) base.cc (10529:05b5a6cf3521)
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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50#include <string>
51
52#include "arch/tlb.hh"
53#include "base/loader/symtab.hh"
54#include "base/cprintf.hh"
55#include "base/misc.hh"
56#include "base/output.hh"
57#include "base/trace.hh"
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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50#include <string>
51
52#include "arch/tlb.hh"
53#include "base/loader/symtab.hh"
54#include "base/cprintf.hh"
55#include "base/misc.hh"
56#include "base/output.hh"
57#include "base/trace.hh"
58#include "cpu/base.hh"
59#include "cpu/checker/cpu.hh"
58#include "cpu/checker/cpu.hh"
59#include "cpu/base.hh"
60#include "cpu/cpuevent.hh"
61#include "cpu/profile.hh"
62#include "cpu/thread_context.hh"
60#include "cpu/cpuevent.hh"
61#include "cpu/profile.hh"
62#include "cpu/thread_context.hh"
63#include "debug/Mwait.hh"
63#include "debug/SyscallVerbose.hh"
64#include "debug/SyscallVerbose.hh"
65#include "mem/page_table.hh"
64#include "params/BaseCPU.hh"
65#include "sim/full_system.hh"
66#include "sim/process.hh"
67#include "sim/sim_events.hh"
68#include "sim/sim_exit.hh"
69#include "sim/system.hh"
70
71// Hack

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118
119BaseCPU::BaseCPU(Params *p, bool is_checker)
120 : MemObject(p), instCnt(0), _cpuId(p->cpu_id), _socketId(p->socket_id),
121 _instMasterId(p->system->getMasterId(name() + ".inst")),
122 _dataMasterId(p->system->getMasterId(name() + ".data")),
123 _taskId(ContextSwitchTaskId::Unknown), _pid(Request::invldPid),
124 _switchedOut(p->switched_out), _cacheLineSize(p->system->cacheLineSize()),
125 interrupts(p->interrupts), profileEvent(NULL),
66#include "params/BaseCPU.hh"
67#include "sim/full_system.hh"
68#include "sim/process.hh"
69#include "sim/sim_events.hh"
70#include "sim/sim_exit.hh"
71#include "sim/system.hh"
72
73// Hack

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120
121BaseCPU::BaseCPU(Params *p, bool is_checker)
122 : MemObject(p), instCnt(0), _cpuId(p->cpu_id), _socketId(p->socket_id),
123 _instMasterId(p->system->getMasterId(name() + ".inst")),
124 _dataMasterId(p->system->getMasterId(name() + ".data")),
125 _taskId(ContextSwitchTaskId::Unknown), _pid(Request::invldPid),
126 _switchedOut(p->switched_out), _cacheLineSize(p->system->cacheLineSize()),
127 interrupts(p->interrupts), profileEvent(NULL),
126 numThreads(p->numThreads), system(p->system)
128 numThreads(p->numThreads), system(p->system),
129 addressMonitor()
127{
128 // if Python did not provide a valid ID, do it here
129 if (_cpuId == -1 ) {
130 _cpuId = cpuList.size();
131 }
132
133 // add self to global list of CPUs
134 cpuList.push_back(this);

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256BaseCPU::~BaseCPU()
257{
258 delete profileEvent;
259 delete[] comLoadEventQueue;
260 delete[] comInstEventQueue;
261}
262
263void
130{
131 // if Python did not provide a valid ID, do it here
132 if (_cpuId == -1 ) {
133 _cpuId = cpuList.size();
134 }
135
136 // add self to global list of CPUs
137 cpuList.push_back(this);

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259BaseCPU::~BaseCPU()
260{
261 delete profileEvent;
262 delete[] comLoadEventQueue;
263 delete[] comInstEventQueue;
264}
265
266void
267BaseCPU::armMonitor(Addr address)
268{
269 addressMonitor.armed = true;
270 addressMonitor.vAddr = address;
271 addressMonitor.pAddr = 0x0;
272 DPRINTF(Mwait,"Armed monitor (vAddr=0x%lx)\n", address);
273}
274
275bool
276BaseCPU::mwait(PacketPtr pkt)
277{
278 if(addressMonitor.gotWakeup == false) {
279 int block_size = cacheLineSize();
280 uint64_t mask = ~((uint64_t)(block_size - 1));
281
282 assert(pkt->req->hasPaddr());
283 addressMonitor.pAddr = pkt->getAddr() & mask;
284 addressMonitor.waiting = true;
285
286 DPRINTF(Mwait,"mwait called (vAddr=0x%lx, line's paddr=0x%lx)\n",
287 addressMonitor.vAddr, addressMonitor.pAddr);
288 return true;
289 } else {
290 addressMonitor.gotWakeup = false;
291 return false;
292 }
293}
294
295void
296BaseCPU::mwaitAtomic(ThreadContext *tc, TheISA::TLB *dtb)
297{
298 Request req;
299 Addr addr = addressMonitor.vAddr;
300 int block_size = cacheLineSize();
301 uint64_t mask = ~((uint64_t)(block_size - 1));
302 int size = block_size;
303
304 //The address of the next line if it crosses a cache line boundary.
305 Addr secondAddr = roundDown(addr + size - 1, block_size);
306
307 if (secondAddr > addr)
308 size = secondAddr - addr;
309
310 req.setVirt(0, addr, size, 0x0, dataMasterId(), tc->instAddr());
311
312 // translate to physical address
313 Fault fault = dtb->translateAtomic(&req, tc, BaseTLB::Read);
314 assert(fault == NoFault);
315
316 addressMonitor.pAddr = req.getPaddr() & mask;
317 addressMonitor.waiting = true;
318
319 DPRINTF(Mwait,"mwait called (vAddr=0x%lx, line's paddr=0x%lx)\n",
320 addressMonitor.vAddr, addressMonitor.pAddr);
321}
322
323void
264BaseCPU::init()
265{
266 if (!params()->switched_out) {
267 registerThreadContexts();
268
269 verifyMemoryMode();
270 }
271}

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613BaseCPU::scheduleInstStop(ThreadID tid, Counter insts, const char *cause)
614{
615 const Tick now(comInstEventQueue[tid]->getCurTick());
616 Event *event(new LocalSimLoopExitEvent(cause, 0));
617
618 comInstEventQueue[tid]->schedule(event, now + insts);
619}
620
324BaseCPU::init()
325{
326 if (!params()->switched_out) {
327 registerThreadContexts();
328
329 verifyMemoryMode();
330 }
331}

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673BaseCPU::scheduleInstStop(ThreadID tid, Counter insts, const char *cause)
674{
675 const Tick now(comInstEventQueue[tid]->getCurTick());
676 Event *event(new LocalSimLoopExitEvent(cause, 0));
677
678 comInstEventQueue[tid]->schedule(event, now + insts);
679}
680
681AddressMonitor::AddressMonitor() {
682 armed = false;
683 waiting = false;
684 gotWakeup = false;
685}
686
687bool AddressMonitor::doMonitor(PacketPtr pkt) {
688 assert(pkt->req->hasPaddr());
689 if(armed && waiting) {
690 if(pAddr == pkt->getAddr()) {
691 DPRINTF(Mwait,"pAddr=0x%lx invalidated: waking up core\n",
692 pkt->getAddr());
693 waiting = false;
694 return true;
695 }
696 }
697 return false;
698}
699
621void
622BaseCPU::scheduleLoadStop(ThreadID tid, Counter loads, const char *cause)
623{
624 const Tick now(comLoadEventQueue[tid]->getCurTick());
625 Event *event(new LocalSimLoopExitEvent(cause, 0));
626
627 comLoadEventQueue[tid]->schedule(event, now + loads);
628}

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701BaseCPU::scheduleLoadStop(ThreadID tid, Counter loads, const char *cause)
702{
703 const Tick now(comLoadEventQueue[tid]->getCurTick());
704 Event *event(new LocalSimLoopExitEvent(cause, 0));
705
706 comLoadEventQueue[tid]->schedule(event, now + loads);
707}

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