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< * Copyright (c) 2011 ARM Limited
< * All rights reserved
< *
< * The license below extends only to copyright in the software and shall
< * not be construed as granting a license to any other intellectual
< * property including but not limited to intellectual property relating
< * to a hardware implementation of the functionality of the software
< * licensed hereunder. You may use the software subject to the license
< * terms below provided that you ensure that this notice is replicated
< * unmodified and in its entirety in all distributions of the software,
< * modified or unmodified, in source code or in binary form.
< *
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< #include "config/use_checker.hh"
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< #if USE_CHECKER
< #include "cpu/checker/cpu.hh"
< #endif
<
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< #if FULL_SYSTEM
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< #else
< BaseCPU::BaseCPU(Params *p)
< : MemObject(p), clock(p->clock), _cpuId(p->cpu_id),
< numThreads(p->numThreads), system(p->system),
< phase(p->phase)
< #endif
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< const string fname = csprintf("ftrace.%s", name());
< functionTraceStream = simout.find(fname);
< if (!functionTraceStream)
< functionTraceStream = simout.create(fname);
<
---
> functionTraceStream = simout.find(csprintf("ftrace.%s", name()));
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< #if FULL_SYSTEM
< // Check if CPU model has interrupts connected. The CheckerCPU
< // cannot take interrupts directly for example.
< if (interrupts)
< interrupts->setCPU(this);
---
> interrupts->setCPU(this);
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> #if FULL_SYSTEM
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< new CPUProgressEvent(this, num_ticks);
---
> Event *event;
> event = new CPUProgressEvent(this, num_ticks);
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< BaseCPU::takeOverFrom(BaseCPU *oldCPU)
---
> BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc)
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< Port *ic = getPort("icache_port");
< Port *dc = getPort("dcache_port");
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<
< #if USE_CHECKER
< Port *old_checker_itb_port, *old_checker_dtb_port;
< Port *new_checker_itb_port, *new_checker_dtb_port;
<
< CheckerCPU *oldChecker =
< dynamic_cast<CheckerCPU*>(oldTC->getCheckerCpuPtr());
< CheckerCPU *newChecker =
< dynamic_cast<CheckerCPU*>(newTC->getCheckerCpuPtr());
< old_checker_itb_port = oldChecker->getITBPtr()->getPort();
< old_checker_dtb_port = oldChecker->getDTBPtr()->getPort();
< new_checker_itb_port = newChecker->getITBPtr()->getPort();
< new_checker_dtb_port = newChecker->getDTBPtr()->getPort();
<
< // Move over any table walker ports if they exist for checker
< if (new_checker_itb_port && !new_checker_itb_port->isConnected()) {
< assert(old_checker_itb_port);
< Port *peer = old_checker_itb_port->getPeer();;
< new_checker_itb_port->setPeer(peer);
< peer->setPeer(new_checker_itb_port);
< }
< if (new_checker_dtb_port && !new_checker_dtb_port->isConnected()) {
< assert(old_checker_dtb_port);
< Port *peer = old_checker_dtb_port->getPeer();;
< new_checker_dtb_port->setPeer(peer);
< peer->setPeer(new_checker_dtb_port);
< }
< #endif
<
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< #if FULL_SYSTEM
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> #if FULL_SYSTEM
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> #endif // FULL_SYSTEM
>
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< #endif // FULL_SYSTEM
<
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<
< bool
< BaseCPU::CpuPort::recvTiming(PacketPtr pkt)
< {
< panic("BaseCPU doesn't expect recvTiming callback!");
< return true;
< }
<
< void
< BaseCPU::CpuPort::recvRetry()
< {
< panic("BaseCPU doesn't expect recvRetry callback!");
< }
<
< Tick
< BaseCPU::CpuPort::recvAtomic(PacketPtr pkt)
< {
< panic("BaseCPU doesn't expect recvAtomic callback!");
< return curTick();
< }
<
< void
< BaseCPU::CpuPort::recvFunctional(PacketPtr pkt)
< {
< // No internal storage to update (in the general case). In the
< // long term this should never be called, but that assumed a split
< // into master/slave and request/response.
< }
<
< void
< BaseCPU::CpuPort::recvRangeChange()
< {
< }