1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 * Nathan Binkert
43 * Rick Strong
44 */
45
46#include <iostream>
47#include <sstream>
48#include <string>
49
50#include "arch/tlb.hh"
51#include "base/loader/symtab.hh"
52#include "base/cprintf.hh"
53#include "base/misc.hh"
54#include "base/output.hh"
55#include "base/trace.hh"
| 1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 * Nathan Binkert
43 * Rick Strong
44 */
45
46#include <iostream>
47#include <sstream>
48#include <string>
49
50#include "arch/tlb.hh"
51#include "base/loader/symtab.hh"
52#include "base/cprintf.hh"
53#include "base/misc.hh"
54#include "base/output.hh"
55#include "base/trace.hh"
|
56#include "config/use_checker.hh"
| |
57#include "cpu/base.hh"
| 56#include "cpu/base.hh"
|
| 57#include "cpu/checker/cpu.hh"
|
58#include "cpu/cpuevent.hh"
59#include "cpu/profile.hh"
60#include "cpu/thread_context.hh"
61#include "debug/SyscallVerbose.hh"
62#include "params/BaseCPU.hh"
63#include "sim/full_system.hh"
64#include "sim/process.hh"
65#include "sim/sim_events.hh"
66#include "sim/sim_exit.hh"
67#include "sim/system.hh"
68
| 58#include "cpu/cpuevent.hh"
59#include "cpu/profile.hh"
60#include "cpu/thread_context.hh"
61#include "debug/SyscallVerbose.hh"
62#include "params/BaseCPU.hh"
63#include "sim/full_system.hh"
64#include "sim/process.hh"
65#include "sim/sim_events.hh"
66#include "sim/sim_exit.hh"
67#include "sim/system.hh"
68
|
69#if USE_CHECKER
70#include "cpu/checker/cpu.hh"
71#endif
72
| |
73// Hack
74#include "sim/stat_control.hh"
75
76using namespace std;
77
78vector<BaseCPU *> BaseCPU::cpuList;
79
80// This variable reflects the max number of threads in any CPU. Be
81// careful to only use it once all the CPUs that you care about have
82// been initialized
83int maxThreadsPerCPU = 1;
84
85CPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival)
86 : Event(Event::Progress_Event_Pri), _interval(ival), lastNumInst(0),
87 cpu(_cpu), _repeatEvent(true)
88{
89 if (_interval)
90 cpu->schedule(this, curTick() + _interval);
91}
92
93void
94CPUProgressEvent::process()
95{
96 Counter temp = cpu->totalOps();
97#ifndef NDEBUG
98 double ipc = double(temp - lastNumInst) / (_interval / cpu->ticks(1));
99
100 DPRINTFN("%s progress event, total committed:%i, progress insts committed: "
101 "%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst,
102 ipc);
103 ipc = 0.0;
104#else
105 cprintf("%lli: %s progress event, total committed:%i, progress insts "
106 "committed: %lli\n", curTick(), cpu->name(), temp,
107 temp - lastNumInst);
108#endif
109 lastNumInst = temp;
110
111 if (_repeatEvent)
112 cpu->schedule(this, curTick() + _interval);
113}
114
115const char *
116CPUProgressEvent::description() const
117{
118 return "CPU Progress";
119}
120
121BaseCPU::BaseCPU(Params *p, bool is_checker)
122 : MemObject(p), clock(p->clock), instCnt(0), _cpuId(p->cpu_id),
123 _instMasterId(p->system->getMasterId(name() + ".inst")),
124 _dataMasterId(p->system->getMasterId(name() + ".data")),
125 interrupts(p->interrupts),
126 numThreads(p->numThreads), system(p->system),
127 phase(p->phase)
128{
129// currentTick = curTick();
130
131 // if Python did not provide a valid ID, do it here
132 if (_cpuId == -1 ) {
133 _cpuId = cpuList.size();
134 }
135
136 // add self to global list of CPUs
137 cpuList.push_back(this);
138
139 DPRINTF(SyscallVerbose, "Constructing CPU with id %d\n", _cpuId);
140
141 if (numThreads > maxThreadsPerCPU)
142 maxThreadsPerCPU = numThreads;
143
144 // allocate per-thread instruction-based event queues
145 comInstEventQueue = new EventQueue *[numThreads];
146 for (ThreadID tid = 0; tid < numThreads; ++tid)
147 comInstEventQueue[tid] =
148 new EventQueue("instruction-based event queue");
149
150 //
151 // set up instruction-count-based termination events, if any
152 //
153 if (p->max_insts_any_thread != 0) {
154 const char *cause = "a thread reached the max instruction count";
155 for (ThreadID tid = 0; tid < numThreads; ++tid) {
156 Event *event = new SimLoopExitEvent(cause, 0);
157 comInstEventQueue[tid]->schedule(event, p->max_insts_any_thread);
158 }
159 }
160
161 if (p->max_insts_all_threads != 0) {
162 const char *cause = "all threads reached the max instruction count";
163
164 // allocate & initialize shared downcounter: each event will
165 // decrement this when triggered; simulation will terminate
166 // when counter reaches 0
167 int *counter = new int;
168 *counter = numThreads;
169 for (ThreadID tid = 0; tid < numThreads; ++tid) {
170 Event *event = new CountedExitEvent(cause, *counter);
171 comInstEventQueue[tid]->schedule(event, p->max_insts_all_threads);
172 }
173 }
174
175 // allocate per-thread load-based event queues
176 comLoadEventQueue = new EventQueue *[numThreads];
177 for (ThreadID tid = 0; tid < numThreads; ++tid)
178 comLoadEventQueue[tid] = new EventQueue("load-based event queue");
179
180 //
181 // set up instruction-count-based termination events, if any
182 //
183 if (p->max_loads_any_thread != 0) {
184 const char *cause = "a thread reached the max load count";
185 for (ThreadID tid = 0; tid < numThreads; ++tid) {
186 Event *event = new SimLoopExitEvent(cause, 0);
187 comLoadEventQueue[tid]->schedule(event, p->max_loads_any_thread);
188 }
189 }
190
191 if (p->max_loads_all_threads != 0) {
192 const char *cause = "all threads reached the max load count";
193 // allocate & initialize shared downcounter: each event will
194 // decrement this when triggered; simulation will terminate
195 // when counter reaches 0
196 int *counter = new int;
197 *counter = numThreads;
198 for (ThreadID tid = 0; tid < numThreads; ++tid) {
199 Event *event = new CountedExitEvent(cause, *counter);
200 comLoadEventQueue[tid]->schedule(event, p->max_loads_all_threads);
201 }
202 }
203
204 functionTracingEnabled = false;
205 if (p->function_trace) {
206 const string fname = csprintf("ftrace.%s", name());
207 functionTraceStream = simout.find(fname);
208 if (!functionTraceStream)
209 functionTraceStream = simout.create(fname);
210
211 currentFunctionStart = currentFunctionEnd = 0;
212 functionEntryTick = p->function_trace_start;
213
214 if (p->function_trace_start == 0) {
215 functionTracingEnabled = true;
216 } else {
217 typedef EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace> wrap;
218 Event *event = new wrap(this, true);
219 schedule(event, p->function_trace_start);
220 }
221 }
222
223 // The interrupts should always be present unless this CPU is
224 // switched in later or in case it is a checker CPU
225 if (!params()->defer_registration && !is_checker) {
226 if (interrupts) {
227 interrupts->setCPU(this);
228 } else {
229 fatal("CPU %s has no interrupt controller.\n"
230 "Ensure createInterruptController() is called.\n", name());
231 }
232 }
233
234 if (FullSystem) {
235 profileEvent = NULL;
236 if (params()->profile)
237 profileEvent = new ProfileEvent(this, params()->profile);
238 }
239 tracer = params()->tracer;
240}
241
242void
243BaseCPU::enableFunctionTrace()
244{
245 functionTracingEnabled = true;
246}
247
248BaseCPU::~BaseCPU()
249{
250}
251
252void
253BaseCPU::init()
254{
255 if (!params()->defer_registration)
256 registerThreadContexts();
257}
258
259void
260BaseCPU::startup()
261{
262 if (FullSystem) {
263 if (!params()->defer_registration && profileEvent)
264 schedule(profileEvent, curTick());
265 }
266
267 if (params()->progress_interval) {
268 Tick num_ticks = ticks(params()->progress_interval);
269
270 new CPUProgressEvent(this, num_ticks);
271 }
272}
273
274
275void
276BaseCPU::regStats()
277{
278 using namespace Stats;
279
280 numCycles
281 .name(name() + ".numCycles")
282 .desc("number of cpu cycles simulated")
283 ;
284
285 numWorkItemsStarted
286 .name(name() + ".numWorkItemsStarted")
287 .desc("number of work items this cpu started")
288 ;
289
290 numWorkItemsCompleted
291 .name(name() + ".numWorkItemsCompleted")
292 .desc("number of work items this cpu completed")
293 ;
294
295 int size = threadContexts.size();
296 if (size > 1) {
297 for (int i = 0; i < size; ++i) {
298 stringstream namestr;
299 ccprintf(namestr, "%s.ctx%d", name(), i);
300 threadContexts[i]->regStats(namestr.str());
301 }
302 } else if (size == 1)
303 threadContexts[0]->regStats(name());
304}
305
306Port *
307BaseCPU::getPort(const string &if_name, int idx)
308{
309 // Get the right port based on name. This applies to all the
310 // subclasses of the base CPU and relies on their implementation
311 // of getDataPort and getInstPort. In all cases there methods
312 // return a CpuPort pointer.
313 if (if_name == "dcache_port")
314 return &getDataPort();
315 else if (if_name == "icache_port")
316 return &getInstPort();
317 else
318 panic("CPU %s has no port named %s\n", name(), if_name);
319}
320
321Tick
322BaseCPU::nextCycle()
323{
324 Tick next_tick = curTick() - phase + clock - 1;
325 next_tick -= (next_tick % clock);
326 next_tick += phase;
327 return next_tick;
328}
329
330Tick
331BaseCPU::nextCycle(Tick begin_tick)
332{
333 Tick next_tick = begin_tick;
334 if (next_tick % clock != 0)
335 next_tick = next_tick - (next_tick % clock) + clock;
336 next_tick += phase;
337
338 assert(next_tick >= curTick());
339 return next_tick;
340}
341
342void
343BaseCPU::registerThreadContexts()
344{
345 ThreadID size = threadContexts.size();
346 for (ThreadID tid = 0; tid < size; ++tid) {
347 ThreadContext *tc = threadContexts[tid];
348
349 /** This is so that contextId and cpuId match where there is a
350 * 1cpu:1context relationship. Otherwise, the order of registration
351 * could affect the assignment and cpu 1 could have context id 3, for
352 * example. We may even want to do something like this for SMT so that
353 * cpu 0 has the lowest thread contexts and cpu N has the highest, but
354 * I'll just do this for now
355 */
356 if (numThreads == 1)
357 tc->setContextId(system->registerThreadContext(tc, _cpuId));
358 else
359 tc->setContextId(system->registerThreadContext(tc));
360
361 if (!FullSystem)
362 tc->getProcessPtr()->assignThreadContext(tc->contextId());
363 }
364}
365
366
367int
368BaseCPU::findContext(ThreadContext *tc)
369{
370 ThreadID size = threadContexts.size();
371 for (ThreadID tid = 0; tid < size; ++tid) {
372 if (tc == threadContexts[tid])
373 return tid;
374 }
375 return 0;
376}
377
378void
379BaseCPU::switchOut()
380{
381 if (profileEvent && profileEvent->scheduled())
382 deschedule(profileEvent);
383}
384
385void
386BaseCPU::takeOverFrom(BaseCPU *oldCPU)
387{
388 CpuPort &ic = getInstPort();
389 CpuPort &dc = getDataPort();
390 assert(threadContexts.size() == oldCPU->threadContexts.size());
391
392 _cpuId = oldCPU->cpuId();
393
394 ThreadID size = threadContexts.size();
395 for (ThreadID i = 0; i < size; ++i) {
396 ThreadContext *newTC = threadContexts[i];
397 ThreadContext *oldTC = oldCPU->threadContexts[i];
398
399 newTC->takeOverFrom(oldTC);
400
401 CpuEvent::replaceThreadContext(oldTC, newTC);
402
403 assert(newTC->contextId() == oldTC->contextId());
404 assert(newTC->threadId() == oldTC->threadId());
405 system->replaceThreadContext(newTC, newTC->contextId());
406
407 /* This code no longer works since the zero register (e.g.,
408 * r31 on Alpha) doesn't necessarily contain zero at this
409 * point.
410 if (DTRACE(Context))
411 ThreadContext::compare(oldTC, newTC);
412 */
413
414 Port *old_itb_port, *old_dtb_port, *new_itb_port, *new_dtb_port;
415 old_itb_port = oldTC->getITBPtr()->getPort();
416 old_dtb_port = oldTC->getDTBPtr()->getPort();
417 new_itb_port = newTC->getITBPtr()->getPort();
418 new_dtb_port = newTC->getDTBPtr()->getPort();
419
420 // Move over any table walker ports if they exist
421 if (new_itb_port && !new_itb_port->isConnected()) {
422 assert(old_itb_port);
423 Port *peer = old_itb_port->getPeer();;
424 new_itb_port->setPeer(peer);
425 peer->setPeer(new_itb_port);
426 }
427 if (new_dtb_port && !new_dtb_port->isConnected()) {
428 assert(old_dtb_port);
429 Port *peer = old_dtb_port->getPeer();;
430 new_dtb_port->setPeer(peer);
431 peer->setPeer(new_dtb_port);
432 }
433
| 69// Hack
70#include "sim/stat_control.hh"
71
72using namespace std;
73
74vector<BaseCPU *> BaseCPU::cpuList;
75
76// This variable reflects the max number of threads in any CPU. Be
77// careful to only use it once all the CPUs that you care about have
78// been initialized
79int maxThreadsPerCPU = 1;
80
81CPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival)
82 : Event(Event::Progress_Event_Pri), _interval(ival), lastNumInst(0),
83 cpu(_cpu), _repeatEvent(true)
84{
85 if (_interval)
86 cpu->schedule(this, curTick() + _interval);
87}
88
89void
90CPUProgressEvent::process()
91{
92 Counter temp = cpu->totalOps();
93#ifndef NDEBUG
94 double ipc = double(temp - lastNumInst) / (_interval / cpu->ticks(1));
95
96 DPRINTFN("%s progress event, total committed:%i, progress insts committed: "
97 "%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst,
98 ipc);
99 ipc = 0.0;
100#else
101 cprintf("%lli: %s progress event, total committed:%i, progress insts "
102 "committed: %lli\n", curTick(), cpu->name(), temp,
103 temp - lastNumInst);
104#endif
105 lastNumInst = temp;
106
107 if (_repeatEvent)
108 cpu->schedule(this, curTick() + _interval);
109}
110
111const char *
112CPUProgressEvent::description() const
113{
114 return "CPU Progress";
115}
116
117BaseCPU::BaseCPU(Params *p, bool is_checker)
118 : MemObject(p), clock(p->clock), instCnt(0), _cpuId(p->cpu_id),
119 _instMasterId(p->system->getMasterId(name() + ".inst")),
120 _dataMasterId(p->system->getMasterId(name() + ".data")),
121 interrupts(p->interrupts),
122 numThreads(p->numThreads), system(p->system),
123 phase(p->phase)
124{
125// currentTick = curTick();
126
127 // if Python did not provide a valid ID, do it here
128 if (_cpuId == -1 ) {
129 _cpuId = cpuList.size();
130 }
131
132 // add self to global list of CPUs
133 cpuList.push_back(this);
134
135 DPRINTF(SyscallVerbose, "Constructing CPU with id %d\n", _cpuId);
136
137 if (numThreads > maxThreadsPerCPU)
138 maxThreadsPerCPU = numThreads;
139
140 // allocate per-thread instruction-based event queues
141 comInstEventQueue = new EventQueue *[numThreads];
142 for (ThreadID tid = 0; tid < numThreads; ++tid)
143 comInstEventQueue[tid] =
144 new EventQueue("instruction-based event queue");
145
146 //
147 // set up instruction-count-based termination events, if any
148 //
149 if (p->max_insts_any_thread != 0) {
150 const char *cause = "a thread reached the max instruction count";
151 for (ThreadID tid = 0; tid < numThreads; ++tid) {
152 Event *event = new SimLoopExitEvent(cause, 0);
153 comInstEventQueue[tid]->schedule(event, p->max_insts_any_thread);
154 }
155 }
156
157 if (p->max_insts_all_threads != 0) {
158 const char *cause = "all threads reached the max instruction count";
159
160 // allocate & initialize shared downcounter: each event will
161 // decrement this when triggered; simulation will terminate
162 // when counter reaches 0
163 int *counter = new int;
164 *counter = numThreads;
165 for (ThreadID tid = 0; tid < numThreads; ++tid) {
166 Event *event = new CountedExitEvent(cause, *counter);
167 comInstEventQueue[tid]->schedule(event, p->max_insts_all_threads);
168 }
169 }
170
171 // allocate per-thread load-based event queues
172 comLoadEventQueue = new EventQueue *[numThreads];
173 for (ThreadID tid = 0; tid < numThreads; ++tid)
174 comLoadEventQueue[tid] = new EventQueue("load-based event queue");
175
176 //
177 // set up instruction-count-based termination events, if any
178 //
179 if (p->max_loads_any_thread != 0) {
180 const char *cause = "a thread reached the max load count";
181 for (ThreadID tid = 0; tid < numThreads; ++tid) {
182 Event *event = new SimLoopExitEvent(cause, 0);
183 comLoadEventQueue[tid]->schedule(event, p->max_loads_any_thread);
184 }
185 }
186
187 if (p->max_loads_all_threads != 0) {
188 const char *cause = "all threads reached the max load count";
189 // allocate & initialize shared downcounter: each event will
190 // decrement this when triggered; simulation will terminate
191 // when counter reaches 0
192 int *counter = new int;
193 *counter = numThreads;
194 for (ThreadID tid = 0; tid < numThreads; ++tid) {
195 Event *event = new CountedExitEvent(cause, *counter);
196 comLoadEventQueue[tid]->schedule(event, p->max_loads_all_threads);
197 }
198 }
199
200 functionTracingEnabled = false;
201 if (p->function_trace) {
202 const string fname = csprintf("ftrace.%s", name());
203 functionTraceStream = simout.find(fname);
204 if (!functionTraceStream)
205 functionTraceStream = simout.create(fname);
206
207 currentFunctionStart = currentFunctionEnd = 0;
208 functionEntryTick = p->function_trace_start;
209
210 if (p->function_trace_start == 0) {
211 functionTracingEnabled = true;
212 } else {
213 typedef EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace> wrap;
214 Event *event = new wrap(this, true);
215 schedule(event, p->function_trace_start);
216 }
217 }
218
219 // The interrupts should always be present unless this CPU is
220 // switched in later or in case it is a checker CPU
221 if (!params()->defer_registration && !is_checker) {
222 if (interrupts) {
223 interrupts->setCPU(this);
224 } else {
225 fatal("CPU %s has no interrupt controller.\n"
226 "Ensure createInterruptController() is called.\n", name());
227 }
228 }
229
230 if (FullSystem) {
231 profileEvent = NULL;
232 if (params()->profile)
233 profileEvent = new ProfileEvent(this, params()->profile);
234 }
235 tracer = params()->tracer;
236}
237
238void
239BaseCPU::enableFunctionTrace()
240{
241 functionTracingEnabled = true;
242}
243
244BaseCPU::~BaseCPU()
245{
246}
247
248void
249BaseCPU::init()
250{
251 if (!params()->defer_registration)
252 registerThreadContexts();
253}
254
255void
256BaseCPU::startup()
257{
258 if (FullSystem) {
259 if (!params()->defer_registration && profileEvent)
260 schedule(profileEvent, curTick());
261 }
262
263 if (params()->progress_interval) {
264 Tick num_ticks = ticks(params()->progress_interval);
265
266 new CPUProgressEvent(this, num_ticks);
267 }
268}
269
270
271void
272BaseCPU::regStats()
273{
274 using namespace Stats;
275
276 numCycles
277 .name(name() + ".numCycles")
278 .desc("number of cpu cycles simulated")
279 ;
280
281 numWorkItemsStarted
282 .name(name() + ".numWorkItemsStarted")
283 .desc("number of work items this cpu started")
284 ;
285
286 numWorkItemsCompleted
287 .name(name() + ".numWorkItemsCompleted")
288 .desc("number of work items this cpu completed")
289 ;
290
291 int size = threadContexts.size();
292 if (size > 1) {
293 for (int i = 0; i < size; ++i) {
294 stringstream namestr;
295 ccprintf(namestr, "%s.ctx%d", name(), i);
296 threadContexts[i]->regStats(namestr.str());
297 }
298 } else if (size == 1)
299 threadContexts[0]->regStats(name());
300}
301
302Port *
303BaseCPU::getPort(const string &if_name, int idx)
304{
305 // Get the right port based on name. This applies to all the
306 // subclasses of the base CPU and relies on their implementation
307 // of getDataPort and getInstPort. In all cases there methods
308 // return a CpuPort pointer.
309 if (if_name == "dcache_port")
310 return &getDataPort();
311 else if (if_name == "icache_port")
312 return &getInstPort();
313 else
314 panic("CPU %s has no port named %s\n", name(), if_name);
315}
316
317Tick
318BaseCPU::nextCycle()
319{
320 Tick next_tick = curTick() - phase + clock - 1;
321 next_tick -= (next_tick % clock);
322 next_tick += phase;
323 return next_tick;
324}
325
326Tick
327BaseCPU::nextCycle(Tick begin_tick)
328{
329 Tick next_tick = begin_tick;
330 if (next_tick % clock != 0)
331 next_tick = next_tick - (next_tick % clock) + clock;
332 next_tick += phase;
333
334 assert(next_tick >= curTick());
335 return next_tick;
336}
337
338void
339BaseCPU::registerThreadContexts()
340{
341 ThreadID size = threadContexts.size();
342 for (ThreadID tid = 0; tid < size; ++tid) {
343 ThreadContext *tc = threadContexts[tid];
344
345 /** This is so that contextId and cpuId match where there is a
346 * 1cpu:1context relationship. Otherwise, the order of registration
347 * could affect the assignment and cpu 1 could have context id 3, for
348 * example. We may even want to do something like this for SMT so that
349 * cpu 0 has the lowest thread contexts and cpu N has the highest, but
350 * I'll just do this for now
351 */
352 if (numThreads == 1)
353 tc->setContextId(system->registerThreadContext(tc, _cpuId));
354 else
355 tc->setContextId(system->registerThreadContext(tc));
356
357 if (!FullSystem)
358 tc->getProcessPtr()->assignThreadContext(tc->contextId());
359 }
360}
361
362
363int
364BaseCPU::findContext(ThreadContext *tc)
365{
366 ThreadID size = threadContexts.size();
367 for (ThreadID tid = 0; tid < size; ++tid) {
368 if (tc == threadContexts[tid])
369 return tid;
370 }
371 return 0;
372}
373
374void
375BaseCPU::switchOut()
376{
377 if (profileEvent && profileEvent->scheduled())
378 deschedule(profileEvent);
379}
380
381void
382BaseCPU::takeOverFrom(BaseCPU *oldCPU)
383{
384 CpuPort &ic = getInstPort();
385 CpuPort &dc = getDataPort();
386 assert(threadContexts.size() == oldCPU->threadContexts.size());
387
388 _cpuId = oldCPU->cpuId();
389
390 ThreadID size = threadContexts.size();
391 for (ThreadID i = 0; i < size; ++i) {
392 ThreadContext *newTC = threadContexts[i];
393 ThreadContext *oldTC = oldCPU->threadContexts[i];
394
395 newTC->takeOverFrom(oldTC);
396
397 CpuEvent::replaceThreadContext(oldTC, newTC);
398
399 assert(newTC->contextId() == oldTC->contextId());
400 assert(newTC->threadId() == oldTC->threadId());
401 system->replaceThreadContext(newTC, newTC->contextId());
402
403 /* This code no longer works since the zero register (e.g.,
404 * r31 on Alpha) doesn't necessarily contain zero at this
405 * point.
406 if (DTRACE(Context))
407 ThreadContext::compare(oldTC, newTC);
408 */
409
410 Port *old_itb_port, *old_dtb_port, *new_itb_port, *new_dtb_port;
411 old_itb_port = oldTC->getITBPtr()->getPort();
412 old_dtb_port = oldTC->getDTBPtr()->getPort();
413 new_itb_port = newTC->getITBPtr()->getPort();
414 new_dtb_port = newTC->getDTBPtr()->getPort();
415
416 // Move over any table walker ports if they exist
417 if (new_itb_port && !new_itb_port->isConnected()) {
418 assert(old_itb_port);
419 Port *peer = old_itb_port->getPeer();;
420 new_itb_port->setPeer(peer);
421 peer->setPeer(new_itb_port);
422 }
423 if (new_dtb_port && !new_dtb_port->isConnected()) {
424 assert(old_dtb_port);
425 Port *peer = old_dtb_port->getPeer();;
426 new_dtb_port->setPeer(peer);
427 peer->setPeer(new_dtb_port);
428 }
429
|
434#if USE_CHECKER
435 Port *old_checker_itb_port, *old_checker_dtb_port;
436 Port *new_checker_itb_port, *new_checker_dtb_port;
| 430 // Checker whether or not we have to transfer CheckerCPU
431 // objects over in the switch
432 CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr();
433 CheckerCPU *newChecker = newTC->getCheckerCpuPtr();
434 if (oldChecker && newChecker) {
435 Port *old_checker_itb_port, *old_checker_dtb_port;
436 Port *new_checker_itb_port, *new_checker_dtb_port;
|
437
| 437
|
438 CheckerCPU *oldChecker =
439 dynamic_cast<CheckerCPU*>(oldTC->getCheckerCpuPtr());
440 CheckerCPU *newChecker =
441 dynamic_cast<CheckerCPU*>(newTC->getCheckerCpuPtr());
442 old_checker_itb_port = oldChecker->getITBPtr()->getPort();
443 old_checker_dtb_port = oldChecker->getDTBPtr()->getPort();
444 new_checker_itb_port = newChecker->getITBPtr()->getPort();
445 new_checker_dtb_port = newChecker->getDTBPtr()->getPort();
| 438 old_checker_itb_port = oldChecker->getITBPtr()->getPort();
439 old_checker_dtb_port = oldChecker->getDTBPtr()->getPort();
440 new_checker_itb_port = newChecker->getITBPtr()->getPort();
441 new_checker_dtb_port = newChecker->getDTBPtr()->getPort();
|
446
| 442
|
447 // Move over any table walker ports if they exist for checker
448 if (new_checker_itb_port && !new_checker_itb_port->isConnected()) {
449 assert(old_checker_itb_port);
450 Port *peer = old_checker_itb_port->getPeer();;
451 new_checker_itb_port->setPeer(peer);
452 peer->setPeer(new_checker_itb_port);
| 443 // Move over any table walker ports if they exist for checker
444 if (new_checker_itb_port && !new_checker_itb_port->isConnected()) {
445 assert(old_checker_itb_port);
446 Port *peer = old_checker_itb_port->getPeer();;
447 new_checker_itb_port->setPeer(peer);
448 peer->setPeer(new_checker_itb_port);
449 }
450 if (new_checker_dtb_port && !new_checker_dtb_port->isConnected()) {
451 assert(old_checker_dtb_port);
452 Port *peer = old_checker_dtb_port->getPeer();;
453 new_checker_dtb_port->setPeer(peer);
454 peer->setPeer(new_checker_dtb_port);
455 }
|
453 }
| 456 }
|
454 if (new_checker_dtb_port && !new_checker_dtb_port->isConnected()) {
455 assert(old_checker_dtb_port);
456 Port *peer = old_checker_dtb_port->getPeer();;
457 new_checker_dtb_port->setPeer(peer);
458 peer->setPeer(new_checker_dtb_port);
459 }
460#endif
461
| |
462 }
463
464 interrupts = oldCPU->interrupts;
465 interrupts->setCPU(this);
466
467 if (FullSystem) {
468 for (ThreadID i = 0; i < size; ++i)
469 threadContexts[i]->profileClear();
470
471 if (profileEvent)
472 schedule(profileEvent, curTick());
473 }
474
475 // Connect new CPU to old CPU's memory only if new CPU isn't
476 // connected to anything. Also connect old CPU's memory to new
477 // CPU.
478 if (!ic.isConnected()) {
479 Port *peer = oldCPU->getInstPort().getPeer();
480 ic.setPeer(peer);
481 peer->setPeer(&ic);
482 }
483
484 if (!dc.isConnected()) {
485 Port *peer = oldCPU->getDataPort().getPeer();
486 dc.setPeer(peer);
487 peer->setPeer(&dc);
488 }
489}
490
491
492BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval)
493 : cpu(_cpu), interval(_interval)
494{ }
495
496void
497BaseCPU::ProfileEvent::process()
498{
499 ThreadID size = cpu->threadContexts.size();
500 for (ThreadID i = 0; i < size; ++i) {
501 ThreadContext *tc = cpu->threadContexts[i];
502 tc->profileSample();
503 }
504
505 cpu->schedule(this, curTick() + interval);
506}
507
508void
509BaseCPU::serialize(std::ostream &os)
510{
511 SERIALIZE_SCALAR(instCnt);
512 interrupts->serialize(os);
513}
514
515void
516BaseCPU::unserialize(Checkpoint *cp, const std::string §ion)
517{
518 UNSERIALIZE_SCALAR(instCnt);
519 interrupts->unserialize(cp, section);
520}
521
522void
523BaseCPU::traceFunctionsInternal(Addr pc)
524{
525 if (!debugSymbolTable)
526 return;
527
528 // if pc enters different function, print new function symbol and
529 // update saved range. Otherwise do nothing.
530 if (pc < currentFunctionStart || pc >= currentFunctionEnd) {
531 string sym_str;
532 bool found = debugSymbolTable->findNearestSymbol(pc, sym_str,
533 currentFunctionStart,
534 currentFunctionEnd);
535
536 if (!found) {
537 // no symbol found: use addr as label
538 sym_str = csprintf("0x%x", pc);
539 currentFunctionStart = pc;
540 currentFunctionEnd = pc + 1;
541 }
542
543 ccprintf(*functionTraceStream, " (%d)\n%d: %s",
544 curTick() - functionEntryTick, curTick(), sym_str);
545 functionEntryTick = curTick();
546 }
547}
548
549bool
550BaseCPU::CpuPort::recvTiming(PacketPtr pkt)
551{
552 panic("BaseCPU doesn't expect recvTiming callback!");
553 return true;
554}
555
556void
557BaseCPU::CpuPort::recvRetry()
558{
559 panic("BaseCPU doesn't expect recvRetry callback!");
560}
561
562Tick
563BaseCPU::CpuPort::recvAtomic(PacketPtr pkt)
564{
565 panic("BaseCPU doesn't expect recvAtomic callback!");
566 return curTick();
567}
568
569void
570BaseCPU::CpuPort::recvFunctional(PacketPtr pkt)
571{
572 // No internal storage to update (in the general case). In the
573 // long term this should never be called, but that assumed a split
574 // into master/slave and request/response.
575}
576
577void
578BaseCPU::CpuPort::recvRangeChange()
579{
580}
| 457 }
458
459 interrupts = oldCPU->interrupts;
460 interrupts->setCPU(this);
461
462 if (FullSystem) {
463 for (ThreadID i = 0; i < size; ++i)
464 threadContexts[i]->profileClear();
465
466 if (profileEvent)
467 schedule(profileEvent, curTick());
468 }
469
470 // Connect new CPU to old CPU's memory only if new CPU isn't
471 // connected to anything. Also connect old CPU's memory to new
472 // CPU.
473 if (!ic.isConnected()) {
474 Port *peer = oldCPU->getInstPort().getPeer();
475 ic.setPeer(peer);
476 peer->setPeer(&ic);
477 }
478
479 if (!dc.isConnected()) {
480 Port *peer = oldCPU->getDataPort().getPeer();
481 dc.setPeer(peer);
482 peer->setPeer(&dc);
483 }
484}
485
486
487BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval)
488 : cpu(_cpu), interval(_interval)
489{ }
490
491void
492BaseCPU::ProfileEvent::process()
493{
494 ThreadID size = cpu->threadContexts.size();
495 for (ThreadID i = 0; i < size; ++i) {
496 ThreadContext *tc = cpu->threadContexts[i];
497 tc->profileSample();
498 }
499
500 cpu->schedule(this, curTick() + interval);
501}
502
503void
504BaseCPU::serialize(std::ostream &os)
505{
506 SERIALIZE_SCALAR(instCnt);
507 interrupts->serialize(os);
508}
509
510void
511BaseCPU::unserialize(Checkpoint *cp, const std::string §ion)
512{
513 UNSERIALIZE_SCALAR(instCnt);
514 interrupts->unserialize(cp, section);
515}
516
517void
518BaseCPU::traceFunctionsInternal(Addr pc)
519{
520 if (!debugSymbolTable)
521 return;
522
523 // if pc enters different function, print new function symbol and
524 // update saved range. Otherwise do nothing.
525 if (pc < currentFunctionStart || pc >= currentFunctionEnd) {
526 string sym_str;
527 bool found = debugSymbolTable->findNearestSymbol(pc, sym_str,
528 currentFunctionStart,
529 currentFunctionEnd);
530
531 if (!found) {
532 // no symbol found: use addr as label
533 sym_str = csprintf("0x%x", pc);
534 currentFunctionStart = pc;
535 currentFunctionEnd = pc + 1;
536 }
537
538 ccprintf(*functionTraceStream, " (%d)\n%d: %s",
539 curTick() - functionEntryTick, curTick(), sym_str);
540 functionEntryTick = curTick();
541 }
542}
543
544bool
545BaseCPU::CpuPort::recvTiming(PacketPtr pkt)
546{
547 panic("BaseCPU doesn't expect recvTiming callback!");
548 return true;
549}
550
551void
552BaseCPU::CpuPort::recvRetry()
553{
554 panic("BaseCPU doesn't expect recvRetry callback!");
555}
556
557Tick
558BaseCPU::CpuPort::recvAtomic(PacketPtr pkt)
559{
560 panic("BaseCPU doesn't expect recvAtomic callback!");
561 return curTick();
562}
563
564void
565BaseCPU::CpuPort::recvFunctional(PacketPtr pkt)
566{
567 // No internal storage to update (in the general case). In the
568 // long term this should never be called, but that assumed a split
569 // into master/slave and request/response.
570}
571
572void
573BaseCPU::CpuPort::recvRangeChange()
574{
575}
|