1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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291 stringstream namestr;
292 ccprintf(namestr, "%s.ctx%d", name(), i);
293 threadContexts[i]->regStats(namestr.str());
294 }
295 } else if (size == 1)
296 threadContexts[0]->regStats(name());
297}
298
299Tick
300BaseCPU::nextCycle()
301{
302 Tick next_tick = curTick() - phase + clock - 1;
303 next_tick -= (next_tick % clock);
304 next_tick += phase;
305 return next_tick;
306}

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358{
359 if (profileEvent && profileEvent->scheduled())
360 deschedule(profileEvent);
361}
362
363void
364BaseCPU::takeOverFrom(BaseCPU *oldCPU)
365{
366 Port *ic = getPort("icache_port");
367 Port *dc = getPort("dcache_port");
368 assert(threadContexts.size() == oldCPU->threadContexts.size());
369
370 _cpuId = oldCPU->cpuId();
371
372 ThreadID size = threadContexts.size();
373 for (ThreadID i = 0; i < size; ++i) {
374 ThreadContext *newTC = threadContexts[i];
375 ThreadContext *oldTC = oldCPU->threadContexts[i];

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448
449 if (profileEvent)
450 schedule(profileEvent, curTick());
451 }
452
453 // Connect new CPU to old CPU's memory only if new CPU isn't
454 // connected to anything. Also connect old CPU's memory to new
455 // CPU.
456 if (!ic->isConnected()) {
457 Port *peer = oldCPU->getPort("icache_port")->getPeer();
458 ic->setPeer(peer);
459 peer->setPeer(ic);
460 }
461
462 if (!dc->isConnected()) {
463 Port *peer = oldCPU->getPort("dcache_port")->getPeer();
464 dc->setPeer(peer);
465 peer->setPeer(dc);
466 }
467}
468
469
470BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval)
471 : cpu(_cpu), interval(_interval)
472{ }
473

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