1/*
2 * Copyright (c) 2011-2012,2016-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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133 _switchedOut(p->switched_out), _cacheLineSize(p->system->cacheLineSize()),
134 interrupts(p->interrupts), profileEvent(NULL),
135 numThreads(p->numThreads), system(p->system),
136 functionTraceStream(nullptr), currentFunctionStart(0),
137 currentFunctionEnd(0), functionEntryTick(0),
138 addressMonitor(p->numThreads),
139 syscallRetryLatency(p->syscallRetryLatency),
140 pwrGatingLatency(p->pwr_gating_latency),
141 enterPwrGatingEvent([this]{ enterPwrGating(); }, name())
142{
143 // if Python did not provide a valid ID, do it here
144 if (_cpuId == -1 ) {
145 _cpuId = cpuList.size();
146 }
147
148 // add self to global list of CPUs

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488void
489BaseCPU::schedulePowerGatingEvent()
490{
491 for (auto tc : threadContexts) {
492 if (tc->status() == ThreadContext::Active)
493 return;
494 }
495
496 if (ClockedObject::pwrState() == Enums::PwrState::CLK_GATED) {
497 assert(!enterPwrGatingEvent.scheduled());
498 // Schedule a power gating event when clock gated for the specified
499 // amount of time
500 schedule(enterPwrGatingEvent, clockEdge(pwrGatingLatency));
501 }
502}
503
504int

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531 if (t->status() != ThreadContext::Suspended) {
532 return;
533 }
534 }
535
536 // All CPU threads suspended, enter lower power state for the CPU
537 ClockedObject::pwrState(Enums::PwrState::CLK_GATED);
538
539 //Schedule power gating event when clock gated for a configurable cycles
540 schedule(enterPwrGatingEvent, clockEdge(pwrGatingLatency));
541}
542
543void
544BaseCPU::enterPwrGating(void)
545{
546 ClockedObject::pwrState(Enums::PwrState::OFF);
547}
548

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