1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 * Nathan Binkert
43 * Rick Strong
44 */
45
46#include <iostream>
47#include <sstream>
48#include <string>
49
50#include "arch/tlb.hh"
51#include "base/loader/symtab.hh"
52#include "base/cprintf.hh"
53#include "base/misc.hh"
54#include "base/output.hh"
55#include "base/trace.hh"
56#include "cpu/base.hh"
57#include "cpu/cpuevent.hh"
58#include "cpu/profile.hh"
59#include "cpu/thread_context.hh"
60#include "debug/SyscallVerbose.hh"
61#include "params/BaseCPU.hh"
62#include "sim/process.hh"
63#include "sim/sim_events.hh"
64#include "sim/sim_exit.hh"
65#include "sim/system.hh"
66
67// Hack
68#include "sim/stat_control.hh"
69
70using namespace std;
71
72vector<BaseCPU *> BaseCPU::cpuList;
73
74// This variable reflects the max number of threads in any CPU. Be
75// careful to only use it once all the CPUs that you care about have
76// been initialized
77int maxThreadsPerCPU = 1;
78
79CPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival)
80 : Event(Event::Progress_Event_Pri), _interval(ival), lastNumInst(0),
81 cpu(_cpu), _repeatEvent(true)
82{
83 if (_interval)
84 cpu->schedule(this, curTick() + _interval);
85}
86
87void
88CPUProgressEvent::process()
89{
90 Counter temp = cpu->totalInstructions();
91#ifndef NDEBUG
92 double ipc = double(temp - lastNumInst) / (_interval / cpu->ticks(1));
93
94 DPRINTFN("%s progress event, total committed:%i, progress insts committed: "
95 "%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst,
96 ipc);
97 ipc = 0.0;
98#else
99 cprintf("%lli: %s progress event, total committed:%i, progress insts "
100 "committed: %lli\n", curTick(), cpu->name(), temp,
101 temp - lastNumInst);
102#endif
103 lastNumInst = temp;
104
105 if (_repeatEvent)
106 cpu->schedule(this, curTick() + _interval);
107}
108
109const char *
110CPUProgressEvent::description() const
111{
112 return "CPU Progress";
113}
114
115#if FULL_SYSTEM
116BaseCPU::BaseCPU(Params *p)
117 : MemObject(p), clock(p->clock), instCnt(0), _cpuId(p->cpu_id),
118 interrupts(p->interrupts),
119 numThreads(p->numThreads), system(p->system),
120 phase(p->phase)
121#else
122BaseCPU::BaseCPU(Params *p)
123 : MemObject(p), clock(p->clock), _cpuId(p->cpu_id),
124 numThreads(p->numThreads), system(p->system),
125 phase(p->phase)
126#endif
127{
128// currentTick = curTick();
129
130 // if Python did not provide a valid ID, do it here
131 if (_cpuId == -1 ) {
132 _cpuId = cpuList.size();
133 }
134
135 // add self to global list of CPUs
136 cpuList.push_back(this);
137
138 DPRINTF(SyscallVerbose, "Constructing CPU with id %d\n", _cpuId);
139
140 if (numThreads > maxThreadsPerCPU)
141 maxThreadsPerCPU = numThreads;
142
143 // allocate per-thread instruction-based event queues
144 comInstEventQueue = new EventQueue *[numThreads];
145 for (ThreadID tid = 0; tid < numThreads; ++tid)
146 comInstEventQueue[tid] =
147 new EventQueue("instruction-based event queue");
148
149 //
150 // set up instruction-count-based termination events, if any
151 //
152 if (p->max_insts_any_thread != 0) {
153 const char *cause = "a thread reached the max instruction count";
154 for (ThreadID tid = 0; tid < numThreads; ++tid) {
155 Event *event = new SimLoopExitEvent(cause, 0);
156 comInstEventQueue[tid]->schedule(event, p->max_insts_any_thread);
157 }
158 }
159
160 if (p->max_insts_all_threads != 0) {
161 const char *cause = "all threads reached the max instruction count";
162
163 // allocate & initialize shared downcounter: each event will
164 // decrement this when triggered; simulation will terminate
165 // when counter reaches 0
166 int *counter = new int;
167 *counter = numThreads;
168 for (ThreadID tid = 0; tid < numThreads; ++tid) {
169 Event *event = new CountedExitEvent(cause, *counter);
170 comInstEventQueue[tid]->schedule(event, p->max_insts_all_threads);
171 }
172 }
173
174 // allocate per-thread load-based event queues
175 comLoadEventQueue = new EventQueue *[numThreads];
176 for (ThreadID tid = 0; tid < numThreads; ++tid)
177 comLoadEventQueue[tid] = new EventQueue("load-based event queue");
178
179 //
180 // set up instruction-count-based termination events, if any
181 //
182 if (p->max_loads_any_thread != 0) {
183 const char *cause = "a thread reached the max load count";
184 for (ThreadID tid = 0; tid < numThreads; ++tid) {
185 Event *event = new SimLoopExitEvent(cause, 0);
186 comLoadEventQueue[tid]->schedule(event, p->max_loads_any_thread);
187 }
188 }
189
190 if (p->max_loads_all_threads != 0) {
191 const char *cause = "all threads reached the max load count";
192 // allocate & initialize shared downcounter: each event will
193 // decrement this when triggered; simulation will terminate
194 // when counter reaches 0
195 int *counter = new int;
196 *counter = numThreads;
197 for (ThreadID tid = 0; tid < numThreads; ++tid) {
198 Event *event = new CountedExitEvent(cause, *counter);
199 comLoadEventQueue[tid]->schedule(event, p->max_loads_all_threads);
200 }
201 }
202
203 functionTracingEnabled = false;
204 if (p->function_trace) {
205 const string fname = csprintf("ftrace.%s", name());
206 functionTraceStream = simout.find(fname);
207 if (!functionTraceStream)
208 functionTraceStream = simout.create(fname);
209
210 currentFunctionStart = currentFunctionEnd = 0;
211 functionEntryTick = p->function_trace_start;
212
213 if (p->function_trace_start == 0) {
214 functionTracingEnabled = true;
215 } else {
216 typedef EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace> wrap;
217 Event *event = new wrap(this, true);
218 schedule(event, p->function_trace_start);
219 }
220 }
221#if FULL_SYSTEM
222 interrupts->setCPU(this);
223
224 profileEvent = NULL;
225 if (params()->profile)
226 profileEvent = new ProfileEvent(this, params()->profile);
227#endif
228 tracer = params()->tracer;
229}
230
231void
232BaseCPU::enableFunctionTrace()
233{
234 functionTracingEnabled = true;
235}
236
237BaseCPU::~BaseCPU()
238{
239}
240
241void
242BaseCPU::init()
243{
244 if (!params()->defer_registration)
245 registerThreadContexts();
246}
247
248void
249BaseCPU::startup()
250{
251#if FULL_SYSTEM
252 if (!params()->defer_registration && profileEvent)
253 schedule(profileEvent, curTick());
254#endif
255
256 if (params()->progress_interval) {
257 Tick num_ticks = ticks(params()->progress_interval);
258
259 new CPUProgressEvent(this, num_ticks);
260 }
261}
262
263
264void
265BaseCPU::regStats()
266{
267 using namespace Stats;
268
269 numCycles
270 .name(name() + ".numCycles")
271 .desc("number of cpu cycles simulated")
272 ;
273
274 numWorkItemsStarted
275 .name(name() + ".numWorkItemsStarted")
276 .desc("number of work items this cpu started")
277 ;
278
279 numWorkItemsCompleted
280 .name(name() + ".numWorkItemsCompleted")
281 .desc("number of work items this cpu completed")
282 ;
283
284 int size = threadContexts.size();
285 if (size > 1) {
286 for (int i = 0; i < size; ++i) {
287 stringstream namestr;
288 ccprintf(namestr, "%s.ctx%d", name(), i);
289 threadContexts[i]->regStats(namestr.str());
290 }
291 } else if (size == 1)
292 threadContexts[0]->regStats(name());
293
294#if FULL_SYSTEM
295#endif
296}
297
298Tick
299BaseCPU::nextCycle()
300{
301 Tick next_tick = curTick() - phase + clock - 1;
302 next_tick -= (next_tick % clock);
303 next_tick += phase;
304 return next_tick;
305}
306
307Tick
308BaseCPU::nextCycle(Tick begin_tick)
309{
310 Tick next_tick = begin_tick;
311 if (next_tick % clock != 0)
312 next_tick = next_tick - (next_tick % clock) + clock;
313 next_tick += phase;
314
315 assert(next_tick >= curTick());
316 return next_tick;
317}
318
319void
320BaseCPU::registerThreadContexts()
321{
322 ThreadID size = threadContexts.size();
323 for (ThreadID tid = 0; tid < size; ++tid) {
324 ThreadContext *tc = threadContexts[tid];
325
326 /** This is so that contextId and cpuId match where there is a
327 * 1cpu:1context relationship. Otherwise, the order of registration
328 * could affect the assignment and cpu 1 could have context id 3, for
329 * example. We may even want to do something like this for SMT so that
330 * cpu 0 has the lowest thread contexts and cpu N has the highest, but
331 * I'll just do this for now
332 */
333 if (numThreads == 1)
334 tc->setContextId(system->registerThreadContext(tc, _cpuId));
335 else
336 tc->setContextId(system->registerThreadContext(tc));
337#if !FULL_SYSTEM
338 tc->getProcessPtr()->assignThreadContext(tc->contextId());
339#endif
340 }
341}
342
343
344int
345BaseCPU::findContext(ThreadContext *tc)
346{
347 ThreadID size = threadContexts.size();
348 for (ThreadID tid = 0; tid < size; ++tid) {
349 if (tc == threadContexts[tid])
350 return tid;
351 }
352 return 0;
353}
354
355void
356BaseCPU::switchOut()
357{
358// panic("This CPU doesn't support sampling!");
359#if FULL_SYSTEM
360 if (profileEvent && profileEvent->scheduled())
361 deschedule(profileEvent);
362#endif
363}
364
365void
366BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc)
367{
368 assert(threadContexts.size() == oldCPU->threadContexts.size());
369
370 _cpuId = oldCPU->cpuId();
371
372 ThreadID size = threadContexts.size();
373 for (ThreadID i = 0; i < size; ++i) {
374 ThreadContext *newTC = threadContexts[i];
375 ThreadContext *oldTC = oldCPU->threadContexts[i];
376
377 newTC->takeOverFrom(oldTC);
378
379 CpuEvent::replaceThreadContext(oldTC, newTC);
380
381 assert(newTC->contextId() == oldTC->contextId());
382 assert(newTC->threadId() == oldTC->threadId());
383 system->replaceThreadContext(newTC, newTC->contextId());
384
385 /* This code no longer works since the zero register (e.g.,
386 * r31 on Alpha) doesn't necessarily contain zero at this
387 * point.
388 if (DTRACE(Context))
389 ThreadContext::compare(oldTC, newTC);
390 */
391
392 Port *old_itb_port, *old_dtb_port, *new_itb_port, *new_dtb_port;
393 old_itb_port = oldTC->getITBPtr()->getPort();
394 old_dtb_port = oldTC->getDTBPtr()->getPort();
395 new_itb_port = newTC->getITBPtr()->getPort();
396 new_dtb_port = newTC->getDTBPtr()->getPort();
397
398 // Move over any table walker ports if they exist
399 if (new_itb_port && !new_itb_port->isConnected()) {
400 assert(old_itb_port);
401 Port *peer = old_itb_port->getPeer();;
402 new_itb_port->setPeer(peer);
403 peer->setPeer(new_itb_port);
404 }
405 if (new_dtb_port && !new_dtb_port->isConnected()) {
406 assert(old_dtb_port);
407 Port *peer = old_dtb_port->getPeer();;
408 new_dtb_port->setPeer(peer);
409 peer->setPeer(new_dtb_port);
410 }
411 }
412
413#if FULL_SYSTEM
414 interrupts = oldCPU->interrupts;
415 interrupts->setCPU(this);
416
417 for (ThreadID i = 0; i < size; ++i)
418 threadContexts[i]->profileClear();
419
420 if (profileEvent)
421 schedule(profileEvent, curTick());
422#endif
423
424 // Connect new CPU to old CPU's memory only if new CPU isn't
425 // connected to anything. Also connect old CPU's memory to new
426 // CPU.
427 if (!ic->isConnected()) {
428 Port *peer = oldCPU->getPort("icache_port")->getPeer();
429 ic->setPeer(peer);
430 peer->setPeer(ic);
431 }
432
433 if (!dc->isConnected()) {
434 Port *peer = oldCPU->getPort("dcache_port")->getPeer();
435 dc->setPeer(peer);
436 peer->setPeer(dc);
437 }
438}
439
440
441#if FULL_SYSTEM
442BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval)
443 : cpu(_cpu), interval(_interval)
444{ }
445
446void
447BaseCPU::ProfileEvent::process()
448{
449 ThreadID size = cpu->threadContexts.size();
450 for (ThreadID i = 0; i < size; ++i) {
451 ThreadContext *tc = cpu->threadContexts[i];
452 tc->profileSample();
453 }
454
455 cpu->schedule(this, curTick() + interval);
456}
457
458void
459BaseCPU::serialize(std::ostream &os)
460{
461 SERIALIZE_SCALAR(instCnt);
462 interrupts->serialize(os);
463}
464
465void
466BaseCPU::unserialize(Checkpoint *cp, const std::string §ion)
467{
468 UNSERIALIZE_SCALAR(instCnt);
469 interrupts->unserialize(cp, section);
470}
471
472#endif // FULL_SYSTEM
473
474void
475BaseCPU::traceFunctionsInternal(Addr pc)
476{
477 if (!debugSymbolTable)
478 return;
479
480 // if pc enters different function, print new function symbol and
481 // update saved range. Otherwise do nothing.
482 if (pc < currentFunctionStart || pc >= currentFunctionEnd) {
483 string sym_str;
484 bool found = debugSymbolTable->findNearestSymbol(pc, sym_str,
485 currentFunctionStart,
486 currentFunctionEnd);
487
488 if (!found) {
489 // no symbol found: use addr as label
490 sym_str = csprintf("0x%x", pc);
491 currentFunctionStart = pc;
492 currentFunctionEnd = pc + 1;
493 }
494
495 ccprintf(*functionTraceStream, " (%d)\n%d: %s",
496 curTick() - functionEntryTick, curTick(), sym_str);
497 functionEntryTick = curTick();
498 }
499}
500
501bool
502BaseCPU::CpuPort::recvTiming(PacketPtr pkt)
503{
504 panic("BaseCPU doesn't expect recvTiming callback!");
505 return true;
506}
507
508void
509BaseCPU::CpuPort::recvRetry()
510{
511 panic("BaseCPU doesn't expect recvRetry callback!");
512}
513
514Tick
515BaseCPU::CpuPort::recvAtomic(PacketPtr pkt)
516{
517 panic("BaseCPU doesn't expect recvAtomic callback!");
518 return curTick();
519}
520
521void
522BaseCPU::CpuPort::recvFunctional(PacketPtr pkt)
523{
524 // No internal storage to update (in the general case). In the
525 // long term this should never be called, but that assumed a split
526 // into master/slave and request/response.
527}
528
529void
530BaseCPU::CpuPort::recvStatusChange(Status status)
531{
532 if (status == RangeChange) {
533 if (!snoopRangeSent) {
534 snoopRangeSent = true;
535 sendStatusChange(Port::RangeChange);
536 }
537 return;
538 }
539
540 panic("BaseCPU doesn't expect recvStatusChange callback!");
541}
542
543void
544BaseCPU::CpuPort::getDeviceAddressRanges(AddrRangeList& resp,
545 bool& snoop)
546{
547 resp.clear();
548 snoop = false;
549}
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 * Nathan Binkert
43 * Rick Strong
44 */
45
46#include <iostream>
47#include <sstream>
48#include <string>
49
50#include "arch/tlb.hh"
51#include "base/loader/symtab.hh"
52#include "base/cprintf.hh"
53#include "base/misc.hh"
54#include "base/output.hh"
55#include "base/trace.hh"
56#include "cpu/base.hh"
57#include "cpu/cpuevent.hh"
58#include "cpu/profile.hh"
59#include "cpu/thread_context.hh"
60#include "debug/SyscallVerbose.hh"
61#include "params/BaseCPU.hh"
62#include "sim/process.hh"
63#include "sim/sim_events.hh"
64#include "sim/sim_exit.hh"
65#include "sim/system.hh"
66
67// Hack
68#include "sim/stat_control.hh"
69
70using namespace std;
71
72vector<BaseCPU *> BaseCPU::cpuList;
73
74// This variable reflects the max number of threads in any CPU. Be
75// careful to only use it once all the CPUs that you care about have
76// been initialized
77int maxThreadsPerCPU = 1;
78
79CPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival)
80 : Event(Event::Progress_Event_Pri), _interval(ival), lastNumInst(0),
81 cpu(_cpu), _repeatEvent(true)
82{
83 if (_interval)
84 cpu->schedule(this, curTick() + _interval);
85}
86
87void
88CPUProgressEvent::process()
89{
90 Counter temp = cpu->totalInstructions();
91#ifndef NDEBUG
92 double ipc = double(temp - lastNumInst) / (_interval / cpu->ticks(1));
93
94 DPRINTFN("%s progress event, total committed:%i, progress insts committed: "
95 "%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst,
96 ipc);
97 ipc = 0.0;
98#else
99 cprintf("%lli: %s progress event, total committed:%i, progress insts "
100 "committed: %lli\n", curTick(), cpu->name(), temp,
101 temp - lastNumInst);
102#endif
103 lastNumInst = temp;
104
105 if (_repeatEvent)
106 cpu->schedule(this, curTick() + _interval);
107}
108
109const char *
110CPUProgressEvent::description() const
111{
112 return "CPU Progress";
113}
114
115#if FULL_SYSTEM
116BaseCPU::BaseCPU(Params *p)
117 : MemObject(p), clock(p->clock), instCnt(0), _cpuId(p->cpu_id),
118 interrupts(p->interrupts),
119 numThreads(p->numThreads), system(p->system),
120 phase(p->phase)
121#else
122BaseCPU::BaseCPU(Params *p)
123 : MemObject(p), clock(p->clock), _cpuId(p->cpu_id),
124 numThreads(p->numThreads), system(p->system),
125 phase(p->phase)
126#endif
127{
128// currentTick = curTick();
129
130 // if Python did not provide a valid ID, do it here
131 if (_cpuId == -1 ) {
132 _cpuId = cpuList.size();
133 }
134
135 // add self to global list of CPUs
136 cpuList.push_back(this);
137
138 DPRINTF(SyscallVerbose, "Constructing CPU with id %d\n", _cpuId);
139
140 if (numThreads > maxThreadsPerCPU)
141 maxThreadsPerCPU = numThreads;
142
143 // allocate per-thread instruction-based event queues
144 comInstEventQueue = new EventQueue *[numThreads];
145 for (ThreadID tid = 0; tid < numThreads; ++tid)
146 comInstEventQueue[tid] =
147 new EventQueue("instruction-based event queue");
148
149 //
150 // set up instruction-count-based termination events, if any
151 //
152 if (p->max_insts_any_thread != 0) {
153 const char *cause = "a thread reached the max instruction count";
154 for (ThreadID tid = 0; tid < numThreads; ++tid) {
155 Event *event = new SimLoopExitEvent(cause, 0);
156 comInstEventQueue[tid]->schedule(event, p->max_insts_any_thread);
157 }
158 }
159
160 if (p->max_insts_all_threads != 0) {
161 const char *cause = "all threads reached the max instruction count";
162
163 // allocate & initialize shared downcounter: each event will
164 // decrement this when triggered; simulation will terminate
165 // when counter reaches 0
166 int *counter = new int;
167 *counter = numThreads;
168 for (ThreadID tid = 0; tid < numThreads; ++tid) {
169 Event *event = new CountedExitEvent(cause, *counter);
170 comInstEventQueue[tid]->schedule(event, p->max_insts_all_threads);
171 }
172 }
173
174 // allocate per-thread load-based event queues
175 comLoadEventQueue = new EventQueue *[numThreads];
176 for (ThreadID tid = 0; tid < numThreads; ++tid)
177 comLoadEventQueue[tid] = new EventQueue("load-based event queue");
178
179 //
180 // set up instruction-count-based termination events, if any
181 //
182 if (p->max_loads_any_thread != 0) {
183 const char *cause = "a thread reached the max load count";
184 for (ThreadID tid = 0; tid < numThreads; ++tid) {
185 Event *event = new SimLoopExitEvent(cause, 0);
186 comLoadEventQueue[tid]->schedule(event, p->max_loads_any_thread);
187 }
188 }
189
190 if (p->max_loads_all_threads != 0) {
191 const char *cause = "all threads reached the max load count";
192 // allocate & initialize shared downcounter: each event will
193 // decrement this when triggered; simulation will terminate
194 // when counter reaches 0
195 int *counter = new int;
196 *counter = numThreads;
197 for (ThreadID tid = 0; tid < numThreads; ++tid) {
198 Event *event = new CountedExitEvent(cause, *counter);
199 comLoadEventQueue[tid]->schedule(event, p->max_loads_all_threads);
200 }
201 }
202
203 functionTracingEnabled = false;
204 if (p->function_trace) {
205 const string fname = csprintf("ftrace.%s", name());
206 functionTraceStream = simout.find(fname);
207 if (!functionTraceStream)
208 functionTraceStream = simout.create(fname);
209
210 currentFunctionStart = currentFunctionEnd = 0;
211 functionEntryTick = p->function_trace_start;
212
213 if (p->function_trace_start == 0) {
214 functionTracingEnabled = true;
215 } else {
216 typedef EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace> wrap;
217 Event *event = new wrap(this, true);
218 schedule(event, p->function_trace_start);
219 }
220 }
221#if FULL_SYSTEM
222 interrupts->setCPU(this);
223
224 profileEvent = NULL;
225 if (params()->profile)
226 profileEvent = new ProfileEvent(this, params()->profile);
227#endif
228 tracer = params()->tracer;
229}
230
231void
232BaseCPU::enableFunctionTrace()
233{
234 functionTracingEnabled = true;
235}
236
237BaseCPU::~BaseCPU()
238{
239}
240
241void
242BaseCPU::init()
243{
244 if (!params()->defer_registration)
245 registerThreadContexts();
246}
247
248void
249BaseCPU::startup()
250{
251#if FULL_SYSTEM
252 if (!params()->defer_registration && profileEvent)
253 schedule(profileEvent, curTick());
254#endif
255
256 if (params()->progress_interval) {
257 Tick num_ticks = ticks(params()->progress_interval);
258
259 new CPUProgressEvent(this, num_ticks);
260 }
261}
262
263
264void
265BaseCPU::regStats()
266{
267 using namespace Stats;
268
269 numCycles
270 .name(name() + ".numCycles")
271 .desc("number of cpu cycles simulated")
272 ;
273
274 numWorkItemsStarted
275 .name(name() + ".numWorkItemsStarted")
276 .desc("number of work items this cpu started")
277 ;
278
279 numWorkItemsCompleted
280 .name(name() + ".numWorkItemsCompleted")
281 .desc("number of work items this cpu completed")
282 ;
283
284 int size = threadContexts.size();
285 if (size > 1) {
286 for (int i = 0; i < size; ++i) {
287 stringstream namestr;
288 ccprintf(namestr, "%s.ctx%d", name(), i);
289 threadContexts[i]->regStats(namestr.str());
290 }
291 } else if (size == 1)
292 threadContexts[0]->regStats(name());
293
294#if FULL_SYSTEM
295#endif
296}
297
298Tick
299BaseCPU::nextCycle()
300{
301 Tick next_tick = curTick() - phase + clock - 1;
302 next_tick -= (next_tick % clock);
303 next_tick += phase;
304 return next_tick;
305}
306
307Tick
308BaseCPU::nextCycle(Tick begin_tick)
309{
310 Tick next_tick = begin_tick;
311 if (next_tick % clock != 0)
312 next_tick = next_tick - (next_tick % clock) + clock;
313 next_tick += phase;
314
315 assert(next_tick >= curTick());
316 return next_tick;
317}
318
319void
320BaseCPU::registerThreadContexts()
321{
322 ThreadID size = threadContexts.size();
323 for (ThreadID tid = 0; tid < size; ++tid) {
324 ThreadContext *tc = threadContexts[tid];
325
326 /** This is so that contextId and cpuId match where there is a
327 * 1cpu:1context relationship. Otherwise, the order of registration
328 * could affect the assignment and cpu 1 could have context id 3, for
329 * example. We may even want to do something like this for SMT so that
330 * cpu 0 has the lowest thread contexts and cpu N has the highest, but
331 * I'll just do this for now
332 */
333 if (numThreads == 1)
334 tc->setContextId(system->registerThreadContext(tc, _cpuId));
335 else
336 tc->setContextId(system->registerThreadContext(tc));
337#if !FULL_SYSTEM
338 tc->getProcessPtr()->assignThreadContext(tc->contextId());
339#endif
340 }
341}
342
343
344int
345BaseCPU::findContext(ThreadContext *tc)
346{
347 ThreadID size = threadContexts.size();
348 for (ThreadID tid = 0; tid < size; ++tid) {
349 if (tc == threadContexts[tid])
350 return tid;
351 }
352 return 0;
353}
354
355void
356BaseCPU::switchOut()
357{
358// panic("This CPU doesn't support sampling!");
359#if FULL_SYSTEM
360 if (profileEvent && profileEvent->scheduled())
361 deschedule(profileEvent);
362#endif
363}
364
365void
366BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc)
367{
368 assert(threadContexts.size() == oldCPU->threadContexts.size());
369
370 _cpuId = oldCPU->cpuId();
371
372 ThreadID size = threadContexts.size();
373 for (ThreadID i = 0; i < size; ++i) {
374 ThreadContext *newTC = threadContexts[i];
375 ThreadContext *oldTC = oldCPU->threadContexts[i];
376
377 newTC->takeOverFrom(oldTC);
378
379 CpuEvent::replaceThreadContext(oldTC, newTC);
380
381 assert(newTC->contextId() == oldTC->contextId());
382 assert(newTC->threadId() == oldTC->threadId());
383 system->replaceThreadContext(newTC, newTC->contextId());
384
385 /* This code no longer works since the zero register (e.g.,
386 * r31 on Alpha) doesn't necessarily contain zero at this
387 * point.
388 if (DTRACE(Context))
389 ThreadContext::compare(oldTC, newTC);
390 */
391
392 Port *old_itb_port, *old_dtb_port, *new_itb_port, *new_dtb_port;
393 old_itb_port = oldTC->getITBPtr()->getPort();
394 old_dtb_port = oldTC->getDTBPtr()->getPort();
395 new_itb_port = newTC->getITBPtr()->getPort();
396 new_dtb_port = newTC->getDTBPtr()->getPort();
397
398 // Move over any table walker ports if they exist
399 if (new_itb_port && !new_itb_port->isConnected()) {
400 assert(old_itb_port);
401 Port *peer = old_itb_port->getPeer();;
402 new_itb_port->setPeer(peer);
403 peer->setPeer(new_itb_port);
404 }
405 if (new_dtb_port && !new_dtb_port->isConnected()) {
406 assert(old_dtb_port);
407 Port *peer = old_dtb_port->getPeer();;
408 new_dtb_port->setPeer(peer);
409 peer->setPeer(new_dtb_port);
410 }
411 }
412
413#if FULL_SYSTEM
414 interrupts = oldCPU->interrupts;
415 interrupts->setCPU(this);
416
417 for (ThreadID i = 0; i < size; ++i)
418 threadContexts[i]->profileClear();
419
420 if (profileEvent)
421 schedule(profileEvent, curTick());
422#endif
423
424 // Connect new CPU to old CPU's memory only if new CPU isn't
425 // connected to anything. Also connect old CPU's memory to new
426 // CPU.
427 if (!ic->isConnected()) {
428 Port *peer = oldCPU->getPort("icache_port")->getPeer();
429 ic->setPeer(peer);
430 peer->setPeer(ic);
431 }
432
433 if (!dc->isConnected()) {
434 Port *peer = oldCPU->getPort("dcache_port")->getPeer();
435 dc->setPeer(peer);
436 peer->setPeer(dc);
437 }
438}
439
440
441#if FULL_SYSTEM
442BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval)
443 : cpu(_cpu), interval(_interval)
444{ }
445
446void
447BaseCPU::ProfileEvent::process()
448{
449 ThreadID size = cpu->threadContexts.size();
450 for (ThreadID i = 0; i < size; ++i) {
451 ThreadContext *tc = cpu->threadContexts[i];
452 tc->profileSample();
453 }
454
455 cpu->schedule(this, curTick() + interval);
456}
457
458void
459BaseCPU::serialize(std::ostream &os)
460{
461 SERIALIZE_SCALAR(instCnt);
462 interrupts->serialize(os);
463}
464
465void
466BaseCPU::unserialize(Checkpoint *cp, const std::string §ion)
467{
468 UNSERIALIZE_SCALAR(instCnt);
469 interrupts->unserialize(cp, section);
470}
471
472#endif // FULL_SYSTEM
473
474void
475BaseCPU::traceFunctionsInternal(Addr pc)
476{
477 if (!debugSymbolTable)
478 return;
479
480 // if pc enters different function, print new function symbol and
481 // update saved range. Otherwise do nothing.
482 if (pc < currentFunctionStart || pc >= currentFunctionEnd) {
483 string sym_str;
484 bool found = debugSymbolTable->findNearestSymbol(pc, sym_str,
485 currentFunctionStart,
486 currentFunctionEnd);
487
488 if (!found) {
489 // no symbol found: use addr as label
490 sym_str = csprintf("0x%x", pc);
491 currentFunctionStart = pc;
492 currentFunctionEnd = pc + 1;
493 }
494
495 ccprintf(*functionTraceStream, " (%d)\n%d: %s",
496 curTick() - functionEntryTick, curTick(), sym_str);
497 functionEntryTick = curTick();
498 }
499}
500
501bool
502BaseCPU::CpuPort::recvTiming(PacketPtr pkt)
503{
504 panic("BaseCPU doesn't expect recvTiming callback!");
505 return true;
506}
507
508void
509BaseCPU::CpuPort::recvRetry()
510{
511 panic("BaseCPU doesn't expect recvRetry callback!");
512}
513
514Tick
515BaseCPU::CpuPort::recvAtomic(PacketPtr pkt)
516{
517 panic("BaseCPU doesn't expect recvAtomic callback!");
518 return curTick();
519}
520
521void
522BaseCPU::CpuPort::recvFunctional(PacketPtr pkt)
523{
524 // No internal storage to update (in the general case). In the
525 // long term this should never be called, but that assumed a split
526 // into master/slave and request/response.
527}
528
529void
530BaseCPU::CpuPort::recvStatusChange(Status status)
531{
532 if (status == RangeChange) {
533 if (!snoopRangeSent) {
534 snoopRangeSent = true;
535 sendStatusChange(Port::RangeChange);
536 }
537 return;
538 }
539
540 panic("BaseCPU doesn't expect recvStatusChange callback!");
541}
542
543void
544BaseCPU::CpuPort::getDeviceAddressRanges(AddrRangeList& resp,
545 bool& snoop)
546{
547 resp.clear();
548 snoop = false;
549}