1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
| 1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
27 */
28
29#ifndef __CPU_ACTIVITY_HH__
30#define __CPU_ACTIVITY_HH__
31
32#include "base/timebuf.hh"
33#include "base/trace.hh"
34
35/**
36 * ActivityRecorder helper class that informs the CPU if it can switch
37 * over to being idle or not. It works by having a time buffer as
38 * long as any time buffer in the CPU, and the CPU and all of its
39 * stages inform the ActivityRecorder when they write to any time
40 * buffer. The ActivityRecorder marks a 1 in the "0" slot of the time
41 * buffer any time a stage writes to a time buffer, and it advances
42 * its time buffer at the same time as all other stages. The
43 * ActivityRecorder also records if a stage has activity to do next
44 * cycle. The recorder keeps a count of these two. Thus any time the
45 * count is non-zero, there is either communication still in flight,
46 * or activity that still must be done, meaning that the CPU can not
47 * idle. If count is zero, then the CPU can safely idle as it has no
48 * more outstanding work to do.
49 */
50class ActivityRecorder {
51 public:
52 ActivityRecorder(int num_stages, int longest_latency, int count);
53
54 /** Records that there is activity this cycle. */
55 void activity();
56
57 /** Advances the activity buffer, decrementing the activityCount
58 * if active communication just left the time buffer, and
59 * determining if there is no activity.
60 */
61 void advance();
62
63 /** Marks a stage as active. */
64 void activateStage(const int idx);
65
66 /** Deactivates a stage. */
67 void deactivateStage(const int idx);
68
69 /** Returns how many things are active within the recorder. */
70 int getActivityCount() { return activityCount; }
71
72 /** Sets the count to a starting value. Can be used to disable
73 * the idling option.
74 */
75 void setActivityCount(int count)
76 { activityCount = count; }
77
78 /** Returns if the CPU should be active. */
79 bool active() { return activityCount; }
80
81 /** Clears the time buffer and the activity count. */
82 void reset();
83
84 /** Debug function to dump the contents of the time buffer. */
85 void dump();
86
87 /** Debug function to ensure that the activity count matches the
88 * contents of the time buffer.
89 */
90 void validate();
91
92 private:
93 /** Time buffer that tracks if any cycles has active communication
94 * in them. It should be as long as the longest communication
95 * latency in the system. Each time any time buffer is written,
96 * the activity buffer should also be written to. The
97 * activityBuffer is advanced along with all the other time
98 * buffers, so it should have a 1 somewhere in it only if there
99 * is active communication in a time buffer.
100 */
101 TimeBuffer<bool> activityBuffer;
102
103 /** Longest latency time buffer in the CPU. */
104 int longestLatency;
105
106 /** Tracks how many stages and cycles of time buffer have
107 * activity. Stages increment this count when they switch to
108 * active, and decrement it when they switch to
109 * inactive. Whenever a cycle that previously had no information
110 * is written in the time buffer, this is incremented. When a
111 * cycle that had information exits the time buffer due to age,
112 * this count is decremented. When the count is 0, there is no
113 * activity in the CPU, and it can be descheduled.
114 */
115 int activityCount;
116
117 /** Number of stages that can be marked as active or inactive. */
118 int numStages;
119
120 /** Records which stages are active/inactive. */
121 bool *stageActive;
122};
123
124#endif // __CPU_ACTIVITY_HH__
| 29 */
30
31#ifndef __CPU_ACTIVITY_HH__
32#define __CPU_ACTIVITY_HH__
33
34#include "base/timebuf.hh"
35#include "base/trace.hh"
36
37/**
38 * ActivityRecorder helper class that informs the CPU if it can switch
39 * over to being idle or not. It works by having a time buffer as
40 * long as any time buffer in the CPU, and the CPU and all of its
41 * stages inform the ActivityRecorder when they write to any time
42 * buffer. The ActivityRecorder marks a 1 in the "0" slot of the time
43 * buffer any time a stage writes to a time buffer, and it advances
44 * its time buffer at the same time as all other stages. The
45 * ActivityRecorder also records if a stage has activity to do next
46 * cycle. The recorder keeps a count of these two. Thus any time the
47 * count is non-zero, there is either communication still in flight,
48 * or activity that still must be done, meaning that the CPU can not
49 * idle. If count is zero, then the CPU can safely idle as it has no
50 * more outstanding work to do.
51 */
52class ActivityRecorder {
53 public:
54 ActivityRecorder(int num_stages, int longest_latency, int count);
55
56 /** Records that there is activity this cycle. */
57 void activity();
58
59 /** Advances the activity buffer, decrementing the activityCount
60 * if active communication just left the time buffer, and
61 * determining if there is no activity.
62 */
63 void advance();
64
65 /** Marks a stage as active. */
66 void activateStage(const int idx);
67
68 /** Deactivates a stage. */
69 void deactivateStage(const int idx);
70
71 /** Returns how many things are active within the recorder. */
72 int getActivityCount() { return activityCount; }
73
74 /** Sets the count to a starting value. Can be used to disable
75 * the idling option.
76 */
77 void setActivityCount(int count)
78 { activityCount = count; }
79
80 /** Returns if the CPU should be active. */
81 bool active() { return activityCount; }
82
83 /** Clears the time buffer and the activity count. */
84 void reset();
85
86 /** Debug function to dump the contents of the time buffer. */
87 void dump();
88
89 /** Debug function to ensure that the activity count matches the
90 * contents of the time buffer.
91 */
92 void validate();
93
94 private:
95 /** Time buffer that tracks if any cycles has active communication
96 * in them. It should be as long as the longest communication
97 * latency in the system. Each time any time buffer is written,
98 * the activity buffer should also be written to. The
99 * activityBuffer is advanced along with all the other time
100 * buffers, so it should have a 1 somewhere in it only if there
101 * is active communication in a time buffer.
102 */
103 TimeBuffer<bool> activityBuffer;
104
105 /** Longest latency time buffer in the CPU. */
106 int longestLatency;
107
108 /** Tracks how many stages and cycles of time buffer have
109 * activity. Stages increment this count when they switch to
110 * active, and decrement it when they switch to
111 * inactive. Whenever a cycle that previously had no information
112 * is written in the time buffer, this is incremented. When a
113 * cycle that had information exits the time buffer due to age,
114 * this count is decremented. When the count is 0, there is no
115 * activity in the CPU, and it can be descheduled.
116 */
117 int activityCount;
118
119 /** Number of stages that can be marked as active or inactive. */
120 int numStages;
121
122 /** Records which stages are active/inactive. */
123 bool *stageActive;
124};
125
126#endif // __CPU_ACTIVITY_HH__
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