1# Copyright (c) 2003-2005 The Regents of The University of Michigan
2# Copyright (c) 2013 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Steve Reinhardt
29
30from m5.params import *
31
32# Set of boolean static instruction properties.
33#
34# Notes:
35# - The IsInteger and IsFloating flags are based on the class of registers
36# accessed by the instruction. Although most instructions will have exactly
37# one of these two flags set, it is possible for an instruction to have
38# neither (e.g., direct unconditional branches, memory barriers) or both
39# (e.g., an FP/int conversion).
40# - If IsMemRef is set, then exactly one of IsLoad or IsStore will be set.
41# - If IsControl is set, then exactly one of IsDirectControl or IsIndirect
42# Control will be set, and exactly one of IsCondControl or IsUncondControl
43# will be set.
44# - IsSerializing, IsMemBarrier, and IsWriteBarrier are implemented as flags
45# since in the current model there's no other way for instructions to inject
46# behavior into the pipeline outside of fetch. Once we go to an exec-in-exec
47# CPU model we should be able to get rid of these flags and implement this
48# behavior via the execute() methods.
49
50class StaticInstFlags(Enum):
51 wrapper_name = 'StaticInstFlags'
52 wrapper_is_struct = True
53 enum_name = 'Flags'
54
55 vals = [
56 'IsNop', # Is a no-op (no effect at all).
57
58 'IsInteger', # References integer regs.
59 'IsFloating', # References FP regs.
60 'IsCC', # References CC regs.
61 'IsVector', # References Vector regs.
62 'IsVectorElem', # References Vector reg elems.
63
64 'IsMemRef', # References memory (load, store, or prefetch)
65 'IsLoad', # Reads from memory (load or prefetch).
66 'IsStore', # Writes to memory.
| 1# Copyright (c) 2003-2005 The Regents of The University of Michigan
2# Copyright (c) 2013 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Steve Reinhardt
29
30from m5.params import *
31
32# Set of boolean static instruction properties.
33#
34# Notes:
35# - The IsInteger and IsFloating flags are based on the class of registers
36# accessed by the instruction. Although most instructions will have exactly
37# one of these two flags set, it is possible for an instruction to have
38# neither (e.g., direct unconditional branches, memory barriers) or both
39# (e.g., an FP/int conversion).
40# - If IsMemRef is set, then exactly one of IsLoad or IsStore will be set.
41# - If IsControl is set, then exactly one of IsDirectControl or IsIndirect
42# Control will be set, and exactly one of IsCondControl or IsUncondControl
43# will be set.
44# - IsSerializing, IsMemBarrier, and IsWriteBarrier are implemented as flags
45# since in the current model there's no other way for instructions to inject
46# behavior into the pipeline outside of fetch. Once we go to an exec-in-exec
47# CPU model we should be able to get rid of these flags and implement this
48# behavior via the execute() methods.
49
50class StaticInstFlags(Enum):
51 wrapper_name = 'StaticInstFlags'
52 wrapper_is_struct = True
53 enum_name = 'Flags'
54
55 vals = [
56 'IsNop', # Is a no-op (no effect at all).
57
58 'IsInteger', # References integer regs.
59 'IsFloating', # References FP regs.
60 'IsCC', # References CC regs.
61 'IsVector', # References Vector regs.
62 'IsVectorElem', # References Vector reg elems.
63
64 'IsMemRef', # References memory (load, store, or prefetch)
65 'IsLoad', # Reads from memory (load or prefetch).
66 'IsStore', # Writes to memory.
|
67 'IsStoreConditional', # Store conditional instruction.
68 'IsIndexed', # Accesses memory with an indexed address
69 # computation
70 'IsInstPrefetch', # Instruction-cache prefetch.
71 'IsDataPrefetch', # Data-cache prefetch.
72
73 'IsControl', # Control transfer instruction.
74 'IsDirectControl', # PC relative control transfer.
75 'IsIndirectControl',# Register indirect control transfer.
76 'IsCondControl', # Conditional control transfer.
77 'IsUncondControl', # Unconditional control transfer.
78 'IsCall', # Subroutine call.
79 'IsReturn', # Subroutine return.
80
81 'IsCondDelaySlot', # Conditional Delay-Slot Instruction
82
83 'IsThreadSync', # Thread synchronization operation.
84
85 'IsSerializing', # Serializes pipeline: won't execute until all
86 # older instructions have committed.
87 'IsSerializeBefore',
88 'IsSerializeAfter',
89 'IsMemBarrier', # Is a memory barrier
90 'IsWriteBarrier', # Is a write barrier
91 'IsReadBarrier', # Is a read barrier
92 'IsERET', # <- Causes the IFU to stall (MIPS ISA)
93
94 'IsNonSpeculative', # Should not be executed speculatively
95 'IsQuiesce', # Is a quiesce instruction
96
97 'IsIprAccess', # Accesses IPRs
98 'IsUnverifiable', # Can't be verified by a checker
99
100 'IsSyscall', # Causes a system call to be emulated in syscall
101 # emulation mode.
102
103 # Flags for microcode
104 'IsMacroop', # Is a macroop containing microops
105 'IsMicroop', # Is a microop
106 'IsDelayedCommit', # This microop doesn't commit right away
107 'IsLastMicroop', # This microop ends a microop sequence
108 'IsFirstMicroop', # This microop begins a microop sequence
109 # This flag doesn't do anything yet
110 'IsMicroBranch', # This microop branches within the microcode for
111 # a macroop
112 'IsDspOp',
113 'IsSquashAfter' # Squash all uncommitted state after executed
114 ]
| 68 'IsStoreConditional', # Store conditional instruction.
69 'IsIndexed', # Accesses memory with an indexed address
70 # computation
71 'IsInstPrefetch', # Instruction-cache prefetch.
72 'IsDataPrefetch', # Data-cache prefetch.
73
74 'IsControl', # Control transfer instruction.
75 'IsDirectControl', # PC relative control transfer.
76 'IsIndirectControl',# Register indirect control transfer.
77 'IsCondControl', # Conditional control transfer.
78 'IsUncondControl', # Unconditional control transfer.
79 'IsCall', # Subroutine call.
80 'IsReturn', # Subroutine return.
81
82 'IsCondDelaySlot', # Conditional Delay-Slot Instruction
83
84 'IsThreadSync', # Thread synchronization operation.
85
86 'IsSerializing', # Serializes pipeline: won't execute until all
87 # older instructions have committed.
88 'IsSerializeBefore',
89 'IsSerializeAfter',
90 'IsMemBarrier', # Is a memory barrier
91 'IsWriteBarrier', # Is a write barrier
92 'IsReadBarrier', # Is a read barrier
93 'IsERET', # <- Causes the IFU to stall (MIPS ISA)
94
95 'IsNonSpeculative', # Should not be executed speculatively
96 'IsQuiesce', # Is a quiesce instruction
97
98 'IsIprAccess', # Accesses IPRs
99 'IsUnverifiable', # Can't be verified by a checker
100
101 'IsSyscall', # Causes a system call to be emulated in syscall
102 # emulation mode.
103
104 # Flags for microcode
105 'IsMacroop', # Is a macroop containing microops
106 'IsMicroop', # Is a microop
107 'IsDelayedCommit', # This microop doesn't commit right away
108 'IsLastMicroop', # This microop ends a microop sequence
109 'IsFirstMicroop', # This microop begins a microop sequence
110 # This flag doesn't do anything yet
111 'IsMicroBranch', # This microop branches within the microcode for
112 # a macroop
113 'IsDspOp',
114 'IsSquashAfter' # Squash all uncommitted state after executed
115 ]
|