SConscript (8809:bb10807da889) | SConscript (8887:20ea02da9c53) |
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1# -*- mode:python -*- 2 3# Copyright (c) 2006 The Regents of The University of Michigan 4# All rights reserved. 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are 8# met: redistributions of source code must retain the above copyright --- 55 unchanged lines hidden (view full) --- 64mem_comp_sig_template = ''' 65virtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN }; 66''' 67 68# Generate a temporary CPU list, including the CheckerCPU if 69# it's enabled. This isn't used for anything else other than StaticInst 70# headers. 71temp_cpu_list = env['CPU_MODELS'][:] | 1# -*- mode:python -*- 2 3# Copyright (c) 2006 The Regents of The University of Michigan 4# All rights reserved. 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are 8# met: redistributions of source code must retain the above copyright --- 55 unchanged lines hidden (view full) --- 64mem_comp_sig_template = ''' 65virtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN }; 66''' 67 68# Generate a temporary CPU list, including the CheckerCPU if 69# it's enabled. This isn't used for anything else other than StaticInst 70# headers. 71temp_cpu_list = env['CPU_MODELS'][:] |
72temp_cpu_list.append('CheckerCPU') 73SimObject('CheckerCPU.py') |
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72 | 74 |
73if env['USE_CHECKER']: 74 temp_cpu_list.append('CheckerCPU') 75 SimObject('CheckerCPU.py') 76 | |
77# Generate header. 78def gen_cpu_exec_signatures(target, source, env): 79 f = open(str(target[0]), 'w') 80 print >> f, ''' 81#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__ 82#define __CPU_STATIC_INST_EXEC_SIGS_HH__ 83''' 84 for cpu in temp_cpu_list: --- 8 unchanged lines hidden (view full) --- 93 return " [GENERATE] static_inst_exec_sigs.hh: " \ 94 + ', '.join(temp_cpu_list) 95 96# Add command to generate header to environment. 97env.Command('static_inst_exec_sigs.hh', (), 98 Action(gen_cpu_exec_signatures, gen_sigs_string, 99 varlist = temp_cpu_list)) 100 | 75# Generate header. 76def gen_cpu_exec_signatures(target, source, env): 77 f = open(str(target[0]), 'w') 78 print >> f, ''' 79#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__ 80#define __CPU_STATIC_INST_EXEC_SIGS_HH__ 81''' 82 for cpu in temp_cpu_list: --- 8 unchanged lines hidden (view full) --- 91 return " [GENERATE] static_inst_exec_sigs.hh: " \ 92 + ', '.join(temp_cpu_list) 93 94# Add command to generate header to environment. 95env.Command('static_inst_exec_sigs.hh', (), 96 Action(gen_cpu_exec_signatures, gen_sigs_string, 97 varlist = temp_cpu_list)) 98 |
101env.Depends('static_inst_exec_sigs.hh', Value(env['USE_CHECKER'])) | |
102env.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS'])) 103 | 99env.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS'])) 100 |
104# List of suppported CPUs by the Checker. Errors out if USE_CHECKER=True 105# and one of these are not being used. 106CheckerSupportedCPUList = ['O3CPU', 'OzoneCPU'] 107 | |
108SimObject('BaseCPU.py') 109SimObject('FuncUnit.py') 110SimObject('ExeTracer.py') 111SimObject('IntelTrace.py') 112SimObject('IntrControl.py') 113SimObject('NativeTrace.py') 114 115Source('activity.cc') --- 12 unchanged lines hidden (view full) --- 128Source('simple_thread.cc') 129Source('thread_context.cc') 130Source('thread_state.cc') 131 132if env['TARGET_ISA'] == 'sparc': 133 SimObject('LegionTrace.py') 134 Source('legiontrace.cc') 135 | 101SimObject('BaseCPU.py') 102SimObject('FuncUnit.py') 103SimObject('ExeTracer.py') 104SimObject('IntelTrace.py') 105SimObject('IntrControl.py') 106SimObject('NativeTrace.py') 107 108Source('activity.cc') --- 12 unchanged lines hidden (view full) --- 121Source('simple_thread.cc') 122Source('thread_context.cc') 123Source('thread_state.cc') 124 125if env['TARGET_ISA'] == 'sparc': 126 SimObject('LegionTrace.py') 127 Source('legiontrace.cc') 128 |
136if env['USE_CHECKER']: 137 SimObject('DummyChecker.py') 138 Source('checker/cpu.cc') 139 Source('dummy_checker_builder.cc') 140 DebugFlag('Checker') 141 checker_supports = False 142 for i in CheckerSupportedCPUList: 143 if i in env['CPU_MODELS']: 144 checker_supports = True 145 if not checker_supports: 146 print "Checker only supports CPU models", 147 for i in CheckerSupportedCPUList: 148 print i, 149 print ", please set USE_CHECKER=False or use one of those CPU models" 150 Exit(1) | 129SimObject('DummyChecker.py') 130Source('checker/cpu.cc') 131Source('dummy_checker_builder.cc') 132DebugFlag('Checker') |
151 152DebugFlag('Activity') 153DebugFlag('Commit') 154DebugFlag('Context') 155DebugFlag('Decode') 156DebugFlag('DynInst') 157DebugFlag('ExecEnable') 158DebugFlag('ExecCPSeq') --- 32 unchanged lines hidden --- | 133 134DebugFlag('Activity') 135DebugFlag('Commit') 136DebugFlag('Context') 137DebugFlag('Decode') 138DebugFlag('DynInst') 139DebugFlag('ExecEnable') 140DebugFlag('ExecCPSeq') --- 32 unchanged lines hidden --- |