SConscript (10259:ebb376f73dd2) SConscript (10319:4207f9bfcceb)
1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright

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30
31Import('*')
32
33if env['TARGET_ISA'] == 'null':
34 SimObject('IntrControl.py')
35 Source('intr_control_noisa.cc')
36 Return()
37
1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright

--- 21 unchanged lines hidden (view full) ---

30
31Import('*')
32
33if env['TARGET_ISA'] == 'null':
34 SimObject('IntrControl.py')
35 Source('intr_control_noisa.cc')
36 Return()
37
38#################################################################
39#
40# Generate StaticInst execute() method signatures.
41#
42# There must be one signature for each CPU model compiled in.
43# Since the set of compiled-in models is flexible, we generate a
44# header containing the appropriate set of signatures on the fly.
45#
46#################################################################
47
48# Template for execute() signature.
49exec_sig_template = '''
50virtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0;
51virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
52{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
53virtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const
54{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN };
55virtual Fault completeAcc(Packet *pkt, %(type)s *xc,
56 Trace::InstRecord *traceData) const
57{ panic("completeAcc not defined!"); M5_DUMMY_RETURN };
58'''
59
60mem_ini_sig_template = '''
61virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
62{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
63virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN };
64'''
65
66mem_comp_sig_template = '''
67virtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN };
68'''
69
70# Generate a temporary CPU list, including the CheckerCPU if
71# it's enabled. This isn't used for anything else other than StaticInst
72# headers.
73temp_cpu_list = env['CPU_MODELS'][:]
74temp_cpu_list.append('CheckerCPU')
75SimObject('CheckerCPU.py')
76
38SimObject('CheckerCPU.py')
39
77# Generate header.
78def gen_cpu_exec_signatures(target, source, env):
79 f = open(str(target[0]), 'w')
80 print >> f, '''
81#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__
82#define __CPU_STATIC_INST_EXEC_SIGS_HH__
83'''
84 for cpu in temp_cpu_list:
85 xc_type = CpuModel.dict[cpu].strings['CPU_exec_context']
86 print >> f, exec_sig_template % { 'type' : xc_type }
87 print >> f, '''
88#endif // __CPU_STATIC_INST_EXEC_SIGS_HH__
89'''
90
91# Generate string that gets printed when header is rebuilt
92def gen_sigs_string(target, source, env):
93 return " [GENERATE] static_inst_exec_sigs.hh: " \
94 + ', '.join(temp_cpu_list)
95
96# Add command to generate header to environment.
97env.Command('static_inst_exec_sigs.hh', (),
98 Action(gen_cpu_exec_signatures, gen_sigs_string,
99 varlist = temp_cpu_list))
100
101env.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS']))
102
103SimObject('BaseCPU.py')
104SimObject('FuncUnit.py')
105SimObject('ExeTracer.py')
106SimObject('IntelTrace.py')
107SimObject('IntrControl.py')
108SimObject('NativeTrace.py')
109SimObject('TimingExpr.py')
110
111Source('activity.cc')
112Source('base.cc')
113Source('cpuevent.cc')
114Source('exetrace.cc')
40SimObject('BaseCPU.py')
41SimObject('FuncUnit.py')
42SimObject('ExeTracer.py')
43SimObject('IntelTrace.py')
44SimObject('IntrControl.py')
45SimObject('NativeTrace.py')
46SimObject('TimingExpr.py')
47
48Source('activity.cc')
49Source('base.cc')
50Source('cpuevent.cc')
51Source('exetrace.cc')
52Source('exec_context.cc')
115Source('func_unit.cc')
116Source('inteltrace.cc')
117Source('intr_control.cc')
118Source('nativetrace.cc')
119Source('pc_event.cc')
120Source('profile.cc')
121Source('quiesce_event.cc')
122Source('reg_class.cc')

--- 55 unchanged lines hidden --- 		53Source('func_unit.cc')
54Source('inteltrace.cc')
55Source('intr_control.cc')
56Source('nativetrace.cc')
57Source('pc_event.cc')
58Source('profile.cc')
59Source('quiesce_event.cc')
60Source('reg_class.cc')

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