1# -*- mode:python -*- 2 3# Copyright (c) 2006 The Regents of The University of Michigan 4# All rights reserved. 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are 8# met: redistributions of source code must retain the above copyright 9# notice, this list of conditions and the following disclaimer; 10# redistributions in binary form must reproduce the above copyright 11# notice, this list of conditions and the following disclaimer in the 12# documentation and/or other materials provided with the distribution; 13# neither the name of the copyright holders nor the names of its 14# contributors may be used to endorse or promote products derived from 15# this software without specific prior written permission. 16# 17# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28# 29# Authors: Steve Reinhardt 30 31Import('*') 32 33if env['TARGET_ISA'] == 'null': 34 SimObject('IntrControl.py') 35 Source('intr_control_noisa.cc') 36 Return() 37
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38#################################################################
39#
40# Generate StaticInst execute() method signatures.
41#
42# There must be one signature for each CPU model compiled in.
43# Since the set of compiled-in models is flexible, we generate a
44# header containing the appropriate set of signatures on the fly.
45#
46#################################################################
47
48# Template for execute() signature.
49exec_sig_template = '''
50virtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0;
51virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
52{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
53virtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const
54{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN };
55virtual Fault completeAcc(Packet *pkt, %(type)s *xc,
56 Trace::InstRecord *traceData) const
57{ panic("completeAcc not defined!"); M5_DUMMY_RETURN };
58'''
59
60mem_ini_sig_template = '''
61virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
62{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
63virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN };
64'''
65
66mem_comp_sig_template = '''
67virtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN };
68'''
69
70# Generate a temporary CPU list, including the CheckerCPU if
71# it's enabled. This isn't used for anything else other than StaticInst
72# headers.
73temp_cpu_list = env['CPU_MODELS'][:]
74temp_cpu_list.append('CheckerCPU')
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38SimObject('CheckerCPU.py') 39
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77# Generate header.
78def gen_cpu_exec_signatures(target, source, env):
79 f = open(str(target[0]), 'w')
80 print >> f, '''
81#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__
82#define __CPU_STATIC_INST_EXEC_SIGS_HH__
83'''
84 for cpu in temp_cpu_list:
85 xc_type = CpuModel.dict[cpu].strings['CPU_exec_context']
86 print >> f, exec_sig_template % { 'type' : xc_type }
87 print >> f, '''
88#endif // __CPU_STATIC_INST_EXEC_SIGS_HH__
89'''
90
91# Generate string that gets printed when header is rebuilt
92def gen_sigs_string(target, source, env):
93 return " [GENERATE] static_inst_exec_sigs.hh: " \
94 + ', '.join(temp_cpu_list)
95
96# Add command to generate header to environment.
97env.Command('static_inst_exec_sigs.hh', (),
98 Action(gen_cpu_exec_signatures, gen_sigs_string,
99 varlist = temp_cpu_list))
100
101env.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS']))
102
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40SimObject('BaseCPU.py') 41SimObject('FuncUnit.py') 42SimObject('ExeTracer.py') 43SimObject('IntelTrace.py') 44SimObject('IntrControl.py') 45SimObject('NativeTrace.py') 46SimObject('TimingExpr.py') 47 48Source('activity.cc') 49Source('base.cc') 50Source('cpuevent.cc') 51Source('exetrace.cc')
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52Source('exec_context.cc') |
53Source('func_unit.cc') 54Source('inteltrace.cc') 55Source('intr_control.cc') 56Source('nativetrace.cc') 57Source('pc_event.cc') 58Source('profile.cc') 59Source('quiesce_event.cc') 60Source('reg_class.cc') 61Source('static_inst.cc') 62Source('simple_thread.cc') 63Source('thread_context.cc') 64Source('thread_state.cc') 65Source('timing_expr.cc') 66 67if env['TARGET_ISA'] == 'sparc': 68 SimObject('LegionTrace.py') 69 Source('legiontrace.cc') 70 71SimObject('DummyChecker.py') 72SimObject('StaticInstFlags.py') 73Source('checker/cpu.cc') 74Source('dummy_checker.cc') 75DebugFlag('Checker') 76 77DebugFlag('Activity') 78DebugFlag('Commit') 79DebugFlag('Context') 80DebugFlag('Decode') 81DebugFlag('DynInst') 82DebugFlag('ExecEnable', 'Filter: Enable exec tracing (no tracing without this)') 83DebugFlag('ExecCPSeq', 'Format: Instruction sequence number') 84DebugFlag('ExecEffAddr', 'Format: Include effective address') 85DebugFlag('ExecFaulting', 'Trace faulting instructions') 86DebugFlag('ExecFetchSeq', 'Format: Fetch sequence number') 87DebugFlag('ExecOpClass', 'Format: Include operand class') 88DebugFlag('ExecRegDelta') 89DebugFlag('ExecResult', 'Format: Include results from execution') 90DebugFlag('ExecSpeculative', 'Format: Include a miss-/speculation flag (-/+)') 91DebugFlag('ExecSymbol', 'Format: Try to include symbol names') 92DebugFlag('ExecThread', 'Format: Include thread ID in trace') 93DebugFlag('ExecTicks', 'Format: Include tick count') 94DebugFlag('ExecMicro', 'Filter: Include microops') 95DebugFlag('ExecMacro', 'Filter: Include macroops') 96DebugFlag('ExecUser', 'Filter: Trace user mode instructions') 97DebugFlag('ExecKernel', 'Filter: Trace kernel mode instructions') 98DebugFlag('ExecAsid', 'Format: Include ASID in trace') 99DebugFlag('Fetch') 100DebugFlag('IntrControl') 101DebugFlag('O3PipeView') 102DebugFlag('PCEvent') 103DebugFlag('Quiesce') 104 105CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr', 106 'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta', 107 'ExecResult', 'ExecSpeculative', 'ExecSymbol', 'ExecThread', 108 'ExecTicks', 'ExecMicro', 'ExecMacro', 'ExecUser', 'ExecKernel', 109 'ExecAsid' ]) 110CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread', 111 'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting', 112 'ExecUser', 'ExecKernel' ]) 113CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread', 114 'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecFaulting', 115 'ExecUser', 'ExecKernel' ])
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