1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright
9# notice, this list of conditions and the following disclaimer;
10# redistributions in binary form must reproduce the above copyright
11# notice, this list of conditions and the following disclaimer in the
12# documentation and/or other materials provided with the distribution;
13# neither the name of the copyright holders nor the names of its
14# contributors may be used to endorse or promote products derived from
15# this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28#
29# Authors: Steve Reinhardt
30
31Import('*')
32
33if env['TARGET_ISA'] == 'null':
34 SimObject('IntrControl.py')
35 Source('intr_control_noisa.cc')
36 Return()
37
38#################################################################
39#
40# Generate StaticInst execute() method signatures.
41#
42# There must be one signature for each CPU model compiled in.
43# Since the set of compiled-in models is flexible, we generate a
44# header containing the appropriate set of signatures on the fly.
45#
46#################################################################
47
48# Template for execute() signature.
49exec_sig_template = '''
50virtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0;
51virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
52{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
53virtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const
54{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN };
55virtual Fault completeAcc(Packet *pkt, %(type)s *xc,
56 Trace::InstRecord *traceData) const
57{ panic("completeAcc not defined!"); M5_DUMMY_RETURN };
58'''
59
60mem_ini_sig_template = '''
61virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
62{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
63virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN };
64'''
65
66mem_comp_sig_template = '''
67virtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN };
68'''
69
70# Generate a temporary CPU list, including the CheckerCPU if
71# it's enabled. This isn't used for anything else other than StaticInst
72# headers.
73temp_cpu_list = env['CPU_MODELS'][:]
74temp_cpu_list.append('CheckerCPU')
75SimObject('CheckerCPU.py')
76
77# Generate header.
78def gen_cpu_exec_signatures(target, source, env):
79 f = open(str(target[0]), 'w')
80 print >> f, '''
81#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__
82#define __CPU_STATIC_INST_EXEC_SIGS_HH__
83'''
84 for cpu in temp_cpu_list:
85 xc_type = CpuModel.dict[cpu].strings['CPU_exec_context']
86 print >> f, exec_sig_template % { 'type' : xc_type }
87 print >> f, '''
88#endif // __CPU_STATIC_INST_EXEC_SIGS_HH__
89'''
90
91# Generate string that gets printed when header is rebuilt
92def gen_sigs_string(target, source, env):
93 return " [GENERATE] static_inst_exec_sigs.hh: " \
94 + ', '.join(temp_cpu_list)
95
96# Add command to generate header to environment.
97env.Command('static_inst_exec_sigs.hh', (),
98 Action(gen_cpu_exec_signatures, gen_sigs_string,
99 varlist = temp_cpu_list))
100
101env.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS']))
102
103SimObject('BaseCPU.py')
104SimObject('FuncUnit.py')
105SimObject('ExeTracer.py')
106SimObject('IntelTrace.py')
107SimObject('IntrControl.py')
108SimObject('NativeTrace.py')
109
110Source('activity.cc')
111Source('base.cc')
112Source('cpuevent.cc')
113Source('exetrace.cc')
114Source('func_unit.cc')
115Source('inteltrace.cc')
116Source('intr_control.cc')
117Source('nativetrace.cc')
118Source('pc_event.cc')
119Source('profile.cc')
120Source('quiesce_event.cc')
| 1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright
9# notice, this list of conditions and the following disclaimer;
10# redistributions in binary form must reproduce the above copyright
11# notice, this list of conditions and the following disclaimer in the
12# documentation and/or other materials provided with the distribution;
13# neither the name of the copyright holders nor the names of its
14# contributors may be used to endorse or promote products derived from
15# this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28#
29# Authors: Steve Reinhardt
30
31Import('*')
32
33if env['TARGET_ISA'] == 'null':
34 SimObject('IntrControl.py')
35 Source('intr_control_noisa.cc')
36 Return()
37
38#################################################################
39#
40# Generate StaticInst execute() method signatures.
41#
42# There must be one signature for each CPU model compiled in.
43# Since the set of compiled-in models is flexible, we generate a
44# header containing the appropriate set of signatures on the fly.
45#
46#################################################################
47
48# Template for execute() signature.
49exec_sig_template = '''
50virtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0;
51virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
52{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
53virtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const
54{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN };
55virtual Fault completeAcc(Packet *pkt, %(type)s *xc,
56 Trace::InstRecord *traceData) const
57{ panic("completeAcc not defined!"); M5_DUMMY_RETURN };
58'''
59
60mem_ini_sig_template = '''
61virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
62{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
63virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN };
64'''
65
66mem_comp_sig_template = '''
67virtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN };
68'''
69
70# Generate a temporary CPU list, including the CheckerCPU if
71# it's enabled. This isn't used for anything else other than StaticInst
72# headers.
73temp_cpu_list = env['CPU_MODELS'][:]
74temp_cpu_list.append('CheckerCPU')
75SimObject('CheckerCPU.py')
76
77# Generate header.
78def gen_cpu_exec_signatures(target, source, env):
79 f = open(str(target[0]), 'w')
80 print >> f, '''
81#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__
82#define __CPU_STATIC_INST_EXEC_SIGS_HH__
83'''
84 for cpu in temp_cpu_list:
85 xc_type = CpuModel.dict[cpu].strings['CPU_exec_context']
86 print >> f, exec_sig_template % { 'type' : xc_type }
87 print >> f, '''
88#endif // __CPU_STATIC_INST_EXEC_SIGS_HH__
89'''
90
91# Generate string that gets printed when header is rebuilt
92def gen_sigs_string(target, source, env):
93 return " [GENERATE] static_inst_exec_sigs.hh: " \
94 + ', '.join(temp_cpu_list)
95
96# Add command to generate header to environment.
97env.Command('static_inst_exec_sigs.hh', (),
98 Action(gen_cpu_exec_signatures, gen_sigs_string,
99 varlist = temp_cpu_list))
100
101env.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS']))
102
103SimObject('BaseCPU.py')
104SimObject('FuncUnit.py')
105SimObject('ExeTracer.py')
106SimObject('IntelTrace.py')
107SimObject('IntrControl.py')
108SimObject('NativeTrace.py')
109
110Source('activity.cc')
111Source('base.cc')
112Source('cpuevent.cc')
113Source('exetrace.cc')
114Source('func_unit.cc')
115Source('inteltrace.cc')
116Source('intr_control.cc')
117Source('nativetrace.cc')
118Source('pc_event.cc')
119Source('profile.cc')
120Source('quiesce_event.cc')
|
121Source('static_inst.cc')
122Source('simple_thread.cc')
123Source('thread_context.cc')
124Source('thread_state.cc')
125
126if env['TARGET_ISA'] == 'sparc':
127 SimObject('LegionTrace.py')
128 Source('legiontrace.cc')
129
130SimObject('DummyChecker.py')
131Source('checker/cpu.cc')
132Source('dummy_checker.cc')
133DebugFlag('Checker')
134
135DebugFlag('Activity')
136DebugFlag('Commit')
137DebugFlag('Context')
138DebugFlag('Decode')
139DebugFlag('DynInst')
140DebugFlag('ExecEnable', 'Filter: Enable exec tracing (no tracing without this)')
141DebugFlag('ExecCPSeq', 'Format: Instruction sequence number')
142DebugFlag('ExecEffAddr', 'Format: Include effective address')
143DebugFlag('ExecFaulting', 'Trace faulting instructions')
144DebugFlag('ExecFetchSeq', 'Format: Fetch sequence number')
145DebugFlag('ExecOpClass', 'Format: Include operand class')
146DebugFlag('ExecRegDelta')
147DebugFlag('ExecResult', 'Format: Include results from execution')
148DebugFlag('ExecSpeculative', 'Format: Include a miss-/speculation flag (-/+)')
149DebugFlag('ExecSymbol', 'Format: Try to include symbol names')
150DebugFlag('ExecThread', 'Format: Include thread ID in trace')
151DebugFlag('ExecTicks', 'Format: Include tick count')
152DebugFlag('ExecMicro', 'Filter: Include microops')
153DebugFlag('ExecMacro', 'Filter: Include macroops')
154DebugFlag('ExecUser', 'Filter: Trace user mode instructions')
155DebugFlag('ExecKernel', 'Filter: Trace kernel mode instructions')
156DebugFlag('ExecAsid', 'Format: Include ASID in trace')
157DebugFlag('Fetch')
158DebugFlag('IntrControl')
159DebugFlag('O3PipeView')
160DebugFlag('PCEvent')
161DebugFlag('Quiesce')
162
163CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr',
164 'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta',
165 'ExecResult', 'ExecSpeculative', 'ExecSymbol', 'ExecThread',
166 'ExecTicks', 'ExecMicro', 'ExecMacro', 'ExecUser', 'ExecKernel',
167 'ExecAsid' ])
168CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
169 'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting',
170 'ExecUser', 'ExecKernel' ])
171CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
172 'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecFaulting',
173 'ExecUser', 'ExecKernel' ])
| 122Source('static_inst.cc')
123Source('simple_thread.cc')
124Source('thread_context.cc')
125Source('thread_state.cc')
126
127if env['TARGET_ISA'] == 'sparc':
128 SimObject('LegionTrace.py')
129 Source('legiontrace.cc')
130
131SimObject('DummyChecker.py')
132Source('checker/cpu.cc')
133Source('dummy_checker.cc')
134DebugFlag('Checker')
135
136DebugFlag('Activity')
137DebugFlag('Commit')
138DebugFlag('Context')
139DebugFlag('Decode')
140DebugFlag('DynInst')
141DebugFlag('ExecEnable', 'Filter: Enable exec tracing (no tracing without this)')
142DebugFlag('ExecCPSeq', 'Format: Instruction sequence number')
143DebugFlag('ExecEffAddr', 'Format: Include effective address')
144DebugFlag('ExecFaulting', 'Trace faulting instructions')
145DebugFlag('ExecFetchSeq', 'Format: Fetch sequence number')
146DebugFlag('ExecOpClass', 'Format: Include operand class')
147DebugFlag('ExecRegDelta')
148DebugFlag('ExecResult', 'Format: Include results from execution')
149DebugFlag('ExecSpeculative', 'Format: Include a miss-/speculation flag (-/+)')
150DebugFlag('ExecSymbol', 'Format: Try to include symbol names')
151DebugFlag('ExecThread', 'Format: Include thread ID in trace')
152DebugFlag('ExecTicks', 'Format: Include tick count')
153DebugFlag('ExecMicro', 'Filter: Include microops')
154DebugFlag('ExecMacro', 'Filter: Include macroops')
155DebugFlag('ExecUser', 'Filter: Trace user mode instructions')
156DebugFlag('ExecKernel', 'Filter: Trace kernel mode instructions')
157DebugFlag('ExecAsid', 'Format: Include ASID in trace')
158DebugFlag('Fetch')
159DebugFlag('IntrControl')
160DebugFlag('O3PipeView')
161DebugFlag('PCEvent')
162DebugFlag('Quiesce')
163
164CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr',
165 'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta',
166 'ExecResult', 'ExecSpeculative', 'ExecSymbol', 'ExecThread',
167 'ExecTicks', 'ExecMicro', 'ExecMacro', 'ExecUser', 'ExecKernel',
168 'ExecAsid' ])
169CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
170 'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting',
171 'ExecUser', 'ExecKernel' ])
172CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
173 'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecFaulting',
174 'ExecUser', 'ExecKernel' ])
|