1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright
9# notice, this list of conditions and the following disclaimer;
10# redistributions in binary form must reproduce the above copyright
11# notice, this list of conditions and the following disclaimer in the
12# documentation and/or other materials provided with the distribution;
13# neither the name of the copyright holders nor the names of its
14# contributors may be used to endorse or promote products derived from
15# this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28#
29# Authors: Steve Reinhardt
30
31Import('*')
32
33if env['TARGET_ISA'] == 'no':
34 Return()
35
36#################################################################
37#
38# Generate StaticInst execute() method signatures.
39#
40# There must be one signature for each CPU model compiled in.
41# Since the set of compiled-in models is flexible, we generate a
42# header containing the appropriate set of signatures on the fly.
43#
44#################################################################
45
46# Template for execute() signature.
47exec_sig_template = '''
48virtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0;
49virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
50{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
51virtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const
52{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN };
53virtual Fault completeAcc(Packet *pkt, %(type)s *xc,
54 Trace::InstRecord *traceData) const
55{ panic("completeAcc not defined!"); M5_DUMMY_RETURN };
56'''
57
58mem_ini_sig_template = '''
59virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
60{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
61virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN };
62'''
63
64mem_comp_sig_template = '''
65virtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN };
66'''
67
68# Generate a temporary CPU list, including the CheckerCPU if
69# it's enabled. This isn't used for anything else other than StaticInst
70# headers.
71temp_cpu_list = env['CPU_MODELS'][:]
72
73if env['USE_CHECKER']:
74 temp_cpu_list.append('CheckerCPU')
75 SimObject('CheckerCPU.py')
76
77# Generate header.
78def gen_cpu_exec_signatures(target, source, env):
79 f = open(str(target[0]), 'w')
80 print >> f, '''
81#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__
82#define __CPU_STATIC_INST_EXEC_SIGS_HH__
83'''
84 for cpu in temp_cpu_list:
85 xc_type = CpuModel.dict[cpu].strings['CPU_exec_context']
86 print >> f, exec_sig_template % { 'type' : xc_type }
87 print >> f, '''
88#endif // __CPU_STATIC_INST_EXEC_SIGS_HH__
89'''
90
91# Generate string that gets printed when header is rebuilt
92def gen_sigs_string(target, source, env):
93 return " [GENERATE] static_inst_exec_sigs.hh: " \
94 + ', '.join(temp_cpu_list)
95
96# Add command to generate header to environment.
97env.Command('static_inst_exec_sigs.hh', (),
98 Action(gen_cpu_exec_signatures, gen_sigs_string,
99 varlist = temp_cpu_list))
100
101env.Depends('static_inst_exec_sigs.hh', Value(env['USE_CHECKER']))
102env.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS']))
103
104# List of suppported CPUs by the Checker. Errors out if USE_CHECKER=True
105# and one of these are not being used.
106CheckerSupportedCPUList = ['O3CPU', 'OzoneCPU']
107
108SimObject('BaseCPU.py')
109SimObject('FuncUnit.py')
110SimObject('ExeTracer.py')
111SimObject('IntelTrace.py')
112SimObject('NativeTrace.py')
113
114Source('activity.cc')
115Source('base.cc')
116Source('cpuevent.cc')
| 1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright
9# notice, this list of conditions and the following disclaimer;
10# redistributions in binary form must reproduce the above copyright
11# notice, this list of conditions and the following disclaimer in the
12# documentation and/or other materials provided with the distribution;
13# neither the name of the copyright holders nor the names of its
14# contributors may be used to endorse or promote products derived from
15# this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28#
29# Authors: Steve Reinhardt
30
31Import('*')
32
33if env['TARGET_ISA'] == 'no':
34 Return()
35
36#################################################################
37#
38# Generate StaticInst execute() method signatures.
39#
40# There must be one signature for each CPU model compiled in.
41# Since the set of compiled-in models is flexible, we generate a
42# header containing the appropriate set of signatures on the fly.
43#
44#################################################################
45
46# Template for execute() signature.
47exec_sig_template = '''
48virtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0;
49virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
50{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
51virtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const
52{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN };
53virtual Fault completeAcc(Packet *pkt, %(type)s *xc,
54 Trace::InstRecord *traceData) const
55{ panic("completeAcc not defined!"); M5_DUMMY_RETURN };
56'''
57
58mem_ini_sig_template = '''
59virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
60{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
61virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN };
62'''
63
64mem_comp_sig_template = '''
65virtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN };
66'''
67
68# Generate a temporary CPU list, including the CheckerCPU if
69# it's enabled. This isn't used for anything else other than StaticInst
70# headers.
71temp_cpu_list = env['CPU_MODELS'][:]
72
73if env['USE_CHECKER']:
74 temp_cpu_list.append('CheckerCPU')
75 SimObject('CheckerCPU.py')
76
77# Generate header.
78def gen_cpu_exec_signatures(target, source, env):
79 f = open(str(target[0]), 'w')
80 print >> f, '''
81#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__
82#define __CPU_STATIC_INST_EXEC_SIGS_HH__
83'''
84 for cpu in temp_cpu_list:
85 xc_type = CpuModel.dict[cpu].strings['CPU_exec_context']
86 print >> f, exec_sig_template % { 'type' : xc_type }
87 print >> f, '''
88#endif // __CPU_STATIC_INST_EXEC_SIGS_HH__
89'''
90
91# Generate string that gets printed when header is rebuilt
92def gen_sigs_string(target, source, env):
93 return " [GENERATE] static_inst_exec_sigs.hh: " \
94 + ', '.join(temp_cpu_list)
95
96# Add command to generate header to environment.
97env.Command('static_inst_exec_sigs.hh', (),
98 Action(gen_cpu_exec_signatures, gen_sigs_string,
99 varlist = temp_cpu_list))
100
101env.Depends('static_inst_exec_sigs.hh', Value(env['USE_CHECKER']))
102env.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS']))
103
104# List of suppported CPUs by the Checker. Errors out if USE_CHECKER=True
105# and one of these are not being used.
106CheckerSupportedCPUList = ['O3CPU', 'OzoneCPU']
107
108SimObject('BaseCPU.py')
109SimObject('FuncUnit.py')
110SimObject('ExeTracer.py')
111SimObject('IntelTrace.py')
112SimObject('NativeTrace.py')
113
114Source('activity.cc')
115Source('base.cc')
116Source('cpuevent.cc')
|
117Source('exetrace.cc')
118Source('func_unit.cc')
119Source('inteltrace.cc')
120Source('nativetrace.cc')
121Source('pc_event.cc')
122Source('quiesce_event.cc')
123Source('static_inst.cc')
124Source('simple_thread.cc')
125Source('thread_context.cc')
126Source('thread_state.cc')
127
128if env['FULL_SYSTEM']:
129 SimObject('IntrControl.py')
130
131 Source('intr_control.cc')
132 Source('profile.cc')
133
134 if env['TARGET_ISA'] == 'sparc':
135 SimObject('LegionTrace.py')
136 Source('legiontrace.cc')
137
138if env['USE_CHECKER']:
139 Source('checker/cpu.cc')
140 DebugFlag('Checker')
141 checker_supports = False
142 for i in CheckerSupportedCPUList:
143 if i in env['CPU_MODELS']:
144 checker_supports = True
145 if not checker_supports:
146 print "Checker only supports CPU models",
147 for i in CheckerSupportedCPUList:
148 print i,
149 print ", please set USE_CHECKER=False or use one of those CPU models"
150 Exit(1)
151
152DebugFlag('Activity')
153DebugFlag('Commit')
154DebugFlag('Context')
155DebugFlag('Decode')
156DebugFlag('DynInst')
157DebugFlag('ExecEnable')
158DebugFlag('ExecCPSeq')
159DebugFlag('ExecEffAddr')
160DebugFlag('ExecFaulting', 'Trace faulting instructions')
161DebugFlag('ExecFetchSeq')
162DebugFlag('ExecOpClass')
163DebugFlag('ExecRegDelta')
164DebugFlag('ExecResult')
165DebugFlag('ExecSpeculative')
166DebugFlag('ExecSymbol')
167DebugFlag('ExecThread')
168DebugFlag('ExecTicks')
169DebugFlag('ExecMicro')
170DebugFlag('ExecMacro')
171DebugFlag('ExecUser')
172DebugFlag('ExecKernel')
173DebugFlag('ExecAsid')
174DebugFlag('Fetch')
175DebugFlag('IntrControl')
176DebugFlag('O3PipeView')
177DebugFlag('PCEvent')
178DebugFlag('Quiesce')
179
180CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr',
181 'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta',
182 'ExecResult', 'ExecSpeculative', 'ExecSymbol', 'ExecThread',
183 'ExecTicks', 'ExecMicro', 'ExecMacro', 'ExecUser', 'ExecKernel',
184 'ExecAsid' ])
185CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
186 'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting',
187 'ExecUser', 'ExecKernel' ])
188CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
189 'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecFaulting',
190 'ExecUser', 'ExecKernel' ])
| 118Source('exetrace.cc')
119Source('func_unit.cc')
120Source('inteltrace.cc')
121Source('nativetrace.cc')
122Source('pc_event.cc')
123Source('quiesce_event.cc')
124Source('static_inst.cc')
125Source('simple_thread.cc')
126Source('thread_context.cc')
127Source('thread_state.cc')
128
129if env['FULL_SYSTEM']:
130 SimObject('IntrControl.py')
131
132 Source('intr_control.cc')
133 Source('profile.cc')
134
135 if env['TARGET_ISA'] == 'sparc':
136 SimObject('LegionTrace.py')
137 Source('legiontrace.cc')
138
139if env['USE_CHECKER']:
140 Source('checker/cpu.cc')
141 DebugFlag('Checker')
142 checker_supports = False
143 for i in CheckerSupportedCPUList:
144 if i in env['CPU_MODELS']:
145 checker_supports = True
146 if not checker_supports:
147 print "Checker only supports CPU models",
148 for i in CheckerSupportedCPUList:
149 print i,
150 print ", please set USE_CHECKER=False or use one of those CPU models"
151 Exit(1)
152
153DebugFlag('Activity')
154DebugFlag('Commit')
155DebugFlag('Context')
156DebugFlag('Decode')
157DebugFlag('DynInst')
158DebugFlag('ExecEnable')
159DebugFlag('ExecCPSeq')
160DebugFlag('ExecEffAddr')
161DebugFlag('ExecFaulting', 'Trace faulting instructions')
162DebugFlag('ExecFetchSeq')
163DebugFlag('ExecOpClass')
164DebugFlag('ExecRegDelta')
165DebugFlag('ExecResult')
166DebugFlag('ExecSpeculative')
167DebugFlag('ExecSymbol')
168DebugFlag('ExecThread')
169DebugFlag('ExecTicks')
170DebugFlag('ExecMicro')
171DebugFlag('ExecMacro')
172DebugFlag('ExecUser')
173DebugFlag('ExecKernel')
174DebugFlag('ExecAsid')
175DebugFlag('Fetch')
176DebugFlag('IntrControl')
177DebugFlag('O3PipeView')
178DebugFlag('PCEvent')
179DebugFlag('Quiesce')
180
181CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr',
182 'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta',
183 'ExecResult', 'ExecSpeculative', 'ExecSymbol', 'ExecThread',
184 'ExecTicks', 'ExecMicro', 'ExecMacro', 'ExecUser', 'ExecKernel',
185 'ExecAsid' ])
186CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
187 'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting',
188 'ExecUser', 'ExecKernel' ])
189CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
190 'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecFaulting',
191 'ExecUser', 'ExecKernel' ])
|