1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright
9# notice, this list of conditions and the following disclaimer;
10# redistributions in binary form must reproduce the above copyright
11# notice, this list of conditions and the following disclaimer in the
12# documentation and/or other materials provided with the distribution;
13# neither the name of the copyright holders nor the names of its
14# contributors may be used to endorse or promote products derived from
15# this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28#
29# Authors: Steve Reinhardt
30
31Import('*')
32
33if env['TARGET_ISA'] == 'null':
34 SimObject('IntrControl.py')
35 Source('intr_control_noisa.cc')
36 Return()
37
| 1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright
9# notice, this list of conditions and the following disclaimer;
10# redistributions in binary form must reproduce the above copyright
11# notice, this list of conditions and the following disclaimer in the
12# documentation and/or other materials provided with the distribution;
13# neither the name of the copyright holders nor the names of its
14# contributors may be used to endorse or promote products derived from
15# this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28#
29# Authors: Steve Reinhardt
30
31Import('*')
32
33if env['TARGET_ISA'] == 'null':
34 SimObject('IntrControl.py')
35 Source('intr_control_noisa.cc')
36 Return()
37
|
38SimObject('CheckerCPU.py')
39
40SimObject('BaseCPU.py')
41SimObject('CPUTracers.py')
42SimObject('FuncUnit.py')
43SimObject('IntrControl.py')
44SimObject('TimingExpr.py')
45
46Source('activity.cc')
47Source('base.cc')
48Source('cpuevent.cc')
49Source('exetrace.cc')
50Source('exec_context.cc')
51Source('func_unit.cc')
52Source('inteltrace.cc')
53Source('intr_control.cc')
54Source('nativetrace.cc')
55Source('pc_event.cc')
56Source('profile.cc')
57Source('quiesce_event.cc')
58Source('reg_class.cc')
59Source('static_inst.cc')
60Source('simple_thread.cc')
61Source('thread_context.cc')
62Source('thread_state.cc')
63Source('timing_expr.cc')
64
65SimObject('DummyChecker.py')
66SimObject('StaticInstFlags.py')
67Source('checker/cpu.cc')
68Source('dummy_checker.cc')
69DebugFlag('Checker')
70
71DebugFlag('Activity')
72DebugFlag('Commit')
73DebugFlag('Context')
74DebugFlag('Decode')
75DebugFlag('DynInst')
76DebugFlag('ExecEnable', 'Filter: Enable exec tracing (no tracing without this)')
77DebugFlag('ExecCPSeq', 'Format: Instruction sequence number')
78DebugFlag('ExecEffAddr', 'Format: Include effective address')
79DebugFlag('ExecFaulting', 'Trace faulting instructions')
80DebugFlag('ExecFetchSeq', 'Format: Fetch sequence number')
81DebugFlag('ExecOpClass', 'Format: Include operand class')
82DebugFlag('ExecRegDelta')
83DebugFlag('ExecResult', 'Format: Include results from execution')
84DebugFlag('ExecSymbol', 'Format: Try to include symbol names')
85DebugFlag('ExecThread', 'Format: Include thread ID in trace')
86DebugFlag('ExecTicks', 'Format: Include tick count')
87DebugFlag('ExecMicro', 'Filter: Include microops')
88DebugFlag('ExecMacro', 'Filter: Include macroops')
89DebugFlag('ExecUser', 'Filter: Trace user mode instructions')
90DebugFlag('ExecKernel', 'Filter: Trace kernel mode instructions')
91DebugFlag('ExecAsid', 'Format: Include ASID in trace')
92DebugFlag('ExecFlags', 'Format: Include instruction flags in trace')
93DebugFlag('Fetch')
94DebugFlag('IntrControl')
95DebugFlag('O3PipeView')
96DebugFlag('PCEvent')
97DebugFlag('Quiesce')
98DebugFlag('Mwait')
99
100CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr',
101 'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta',
102 'ExecResult', 'ExecSymbol', 'ExecThread',
103 'ExecTicks', 'ExecMicro', 'ExecMacro', 'ExecUser', 'ExecKernel',
104 'ExecAsid', 'ExecFlags' ])
105CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
106 'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting',
107 'ExecUser', 'ExecKernel' ])
108CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
109 'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecFaulting',
110 'ExecUser', 'ExecKernel' ])
| 43SimObject('CheckerCPU.py')
44
45SimObject('BaseCPU.py')
46SimObject('CPUTracers.py')
47SimObject('FuncUnit.py')
48SimObject('IntrControl.py')
49SimObject('TimingExpr.py')
50
51Source('activity.cc')
52Source('base.cc')
53Source('cpuevent.cc')
54Source('exetrace.cc')
55Source('exec_context.cc')
56Source('func_unit.cc')
57Source('inteltrace.cc')
58Source('intr_control.cc')
59Source('nativetrace.cc')
60Source('pc_event.cc')
61Source('profile.cc')
62Source('quiesce_event.cc')
63Source('reg_class.cc')
64Source('static_inst.cc')
65Source('simple_thread.cc')
66Source('thread_context.cc')
67Source('thread_state.cc')
68Source('timing_expr.cc')
69
70SimObject('DummyChecker.py')
71SimObject('StaticInstFlags.py')
72Source('checker/cpu.cc')
73Source('dummy_checker.cc')
74DebugFlag('Checker')
75
76DebugFlag('Activity')
77DebugFlag('Commit')
78DebugFlag('Context')
79DebugFlag('Decode')
80DebugFlag('DynInst')
81DebugFlag('ExecEnable', 'Filter: Enable exec tracing (no tracing without this)')
82DebugFlag('ExecCPSeq', 'Format: Instruction sequence number')
83DebugFlag('ExecEffAddr', 'Format: Include effective address')
84DebugFlag('ExecFaulting', 'Trace faulting instructions')
85DebugFlag('ExecFetchSeq', 'Format: Fetch sequence number')
86DebugFlag('ExecOpClass', 'Format: Include operand class')
87DebugFlag('ExecRegDelta')
88DebugFlag('ExecResult', 'Format: Include results from execution')
89DebugFlag('ExecSymbol', 'Format: Try to include symbol names')
90DebugFlag('ExecThread', 'Format: Include thread ID in trace')
91DebugFlag('ExecTicks', 'Format: Include tick count')
92DebugFlag('ExecMicro', 'Filter: Include microops')
93DebugFlag('ExecMacro', 'Filter: Include macroops')
94DebugFlag('ExecUser', 'Filter: Trace user mode instructions')
95DebugFlag('ExecKernel', 'Filter: Trace kernel mode instructions')
96DebugFlag('ExecAsid', 'Format: Include ASID in trace')
97DebugFlag('ExecFlags', 'Format: Include instruction flags in trace')
98DebugFlag('Fetch')
99DebugFlag('IntrControl')
100DebugFlag('O3PipeView')
101DebugFlag('PCEvent')
102DebugFlag('Quiesce')
103DebugFlag('Mwait')
104
105CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr',
106 'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta',
107 'ExecResult', 'ExecSymbol', 'ExecThread',
108 'ExecTicks', 'ExecMicro', 'ExecMacro', 'ExecUser', 'ExecKernel',
109 'ExecAsid', 'ExecFlags' ])
110CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
111 'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting',
112 'ExecUser', 'ExecKernel' ])
113CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
114 'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecFaulting',
115 'ExecUser', 'ExecKernel' ])
|