1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright

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117Source('cpuevent.cc')
118Source('decode.cc')
119Source('exetrace.cc')
120Source('func_unit.cc')
121Source('inteltrace.cc')
122Source('intr_control.cc')
123Source('nativetrace.cc')
124Source('pc_event.cc')
125Source('profile.cc')
126Source('quiesce_event.cc')
127Source('static_inst.cc')
128Source('simple_thread.cc')
129Source('thread_context.cc')
130Source('thread_state.cc')
131
132if env['FULL_SYSTEM']:
133 if env['TARGET_ISA'] == 'sparc':
134 SimObject('LegionTrace.py')
135 Source('legiontrace.cc')
136
137if env['USE_CHECKER']:
138 Source('checker/cpu.cc')
139 DebugFlag('Checker')
140 checker_supports = False

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