BaseCPU.py (9793:6e6cefc1db1f) BaseCPU.py (9849:603e2ed487f3)
1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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46from m5.defines import buildEnv
47from m5.params import *
48from m5.proxy import *
49
50from Bus import CoherentBus
51from InstTracer import InstTracer
52from ExeTracer import ExeTracer
53from MemObject import MemObject
1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 37 unchanged lines hidden (view full) ---

46from m5.defines import buildEnv
47from m5.params import *
48from m5.proxy import *
49
50from Bus import CoherentBus
51from InstTracer import InstTracer
52from ExeTracer import ExeTracer
53from MemObject import MemObject
54from BranchPredictor import BranchPredictor
55from ClockDomain import *
56
57default_tracer = ExeTracer()
58
59if buildEnv['TARGET_ISA'] == 'alpha':
60 from AlphaTLB import AlphaDTB, AlphaITB
61 from AlphaInterrupts import AlphaInterrupts
62 from AlphaISA import AlphaISA

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205 "between CPU models)")
206
207 tracer = Param.InstTracer(default_tracer, "Instruction tracer")
208
209 icache_port = MasterPort("Instruction Port")
210 dcache_port = MasterPort("Data Port")
211 _cached_ports = ['icache_port', 'dcache_port']
212
54from ClockDomain import *
55
56default_tracer = ExeTracer()
57
58if buildEnv['TARGET_ISA'] == 'alpha':
59 from AlphaTLB import AlphaDTB, AlphaITB
60 from AlphaInterrupts import AlphaInterrupts
61 from AlphaISA import AlphaISA

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204 "between CPU models)")
205
206 tracer = Param.InstTracer(default_tracer, "Instruction tracer")
207
208 icache_port = MasterPort("Instruction Port")
209 dcache_port = MasterPort("Data Port")
210 _cached_ports = ['icache_port', 'dcache_port']
211
213 branchPred = Param.BranchPredictor(NULL, "Branch Predictor")
214
215 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
216 _cached_ports += ["itb.walker.port", "dtb.walker.port"]
217
218 _uncached_slave_ports = []
219 _uncached_master_ports = []
220 if buildEnv['TARGET_ISA'] == 'x86':
221 _uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"]
222 _uncached_master_ports += ["interrupts.int_master"]

--- 81 unchanged lines hidden --- 		212 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
213 _cached_ports += ["itb.walker.port", "dtb.walker.port"]
214
215 _uncached_slave_ports = []
216 _uncached_master_ports = []
217 if buildEnv['TARGET_ISA'] == 'x86':
218 _uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"]
219 _uncached_master_ports += ["interrupts.int_master"]

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