BaseCPU.py (9788:5558ee8dd7d9) BaseCPU.py (9793:6e6cefc1db1f)
1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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47from m5.params import *
48from m5.proxy import *
49
50from Bus import CoherentBus
51from InstTracer import InstTracer
52from ExeTracer import ExeTracer
53from MemObject import MemObject
54from BranchPredictor import BranchPredictor
1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 38 unchanged lines hidden (view full) ---

47from m5.params import *
48from m5.proxy import *
49
50from Bus import CoherentBus
51from InstTracer import InstTracer
52from ExeTracer import ExeTracer
53from MemObject import MemObject
54from BranchPredictor import BranchPredictor
55from ClockDomain import *
55
56default_tracer = ExeTracer()
57
58if buildEnv['TARGET_ISA'] == 'alpha':
59 from AlphaTLB import AlphaDTB, AlphaITB
60 from AlphaInterrupts import AlphaInterrupts
61 from AlphaISA import AlphaISA
62 isa_class = AlphaISA

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221 _uncached_master_ports += ["interrupts.int_master"]
222
223 def createInterruptController(self):
224 if buildEnv['TARGET_ISA'] == 'sparc':
225 self.interrupts = SparcInterrupts()
226 elif buildEnv['TARGET_ISA'] == 'alpha':
227 self.interrupts = AlphaInterrupts()
228 elif buildEnv['TARGET_ISA'] == 'x86':
56
57default_tracer = ExeTracer()
58
59if buildEnv['TARGET_ISA'] == 'alpha':
60 from AlphaTLB import AlphaDTB, AlphaITB
61 from AlphaInterrupts import AlphaInterrupts
62 from AlphaISA import AlphaISA
63 isa_class = AlphaISA

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222 _uncached_master_ports += ["interrupts.int_master"]
223
224 def createInterruptController(self):
225 if buildEnv['TARGET_ISA'] == 'sparc':
226 self.interrupts = SparcInterrupts()
227 elif buildEnv['TARGET_ISA'] == 'alpha':
228 self.interrupts = AlphaInterrupts()
229 elif buildEnv['TARGET_ISA'] == 'x86':
229 self.interrupts = X86LocalApic(clock = Parent.clock * 16,
230 self.apic_clk_domain = DerivedClockDomain(clk_domain =
231 Parent.clk_domain,
232 clk_divider = 16)
233 self.interrupts = X86LocalApic(clk_domain = self.apic_clk_domain,
230 pio_addr=0x2000000000000000)
231 _localApic = self.interrupts
232 elif buildEnv['TARGET_ISA'] == 'mips':
233 self.interrupts = MipsInterrupts()
234 elif buildEnv['TARGET_ISA'] == 'arm':
235 self.interrupts = ArmInterrupts()
236 elif buildEnv['TARGET_ISA'] == 'power':
237 self.interrupts = PowerInterrupts()

--- 62 unchanged lines hidden --- 		234 pio_addr=0x2000000000000000)
235 _localApic = self.interrupts
236 elif buildEnv['TARGET_ISA'] == 'mips':
237 self.interrupts = MipsInterrupts()
238 elif buildEnv['TARGET_ISA'] == 'arm':
239 self.interrupts = ArmInterrupts()
240 elif buildEnv['TARGET_ISA'] == 'power':
241 self.interrupts = PowerInterrupts()

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