| BaseCPU.py (9749:cffb82b745cf) | BaseCPU.py (9788:5558ee8dd7d9) |
|---|---|
| 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 267 unchanged lines hidden (view full) --- 276 # Checker doesn't need its own tlb caches because it does 277 # functional accesses only 278 if self.checker != NULL: 279 self._cached_ports += ["checker.itb.walker.port", \ 280 "checker.dtb.walker.port"] 281 282 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 283 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) | 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 267 unchanged lines hidden (view full) --- 276 # Checker doesn't need its own tlb caches because it does 277 # functional accesses only 278 if self.checker != NULL: 279 self._cached_ports += ["checker.itb.walker.port", \ 280 "checker.dtb.walker.port"] 281 282 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 283 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) |
| 284 # Override the default bus clock of 1 GHz and uses the CPU 285 # clock for the L1-to-L2 bus, and also set a width of 32 bytes 286 # (256-bits), which is four times that of the default bus. 287 self.toL2Bus = CoherentBus(clock = Parent.clock, width = 32) | 284 # Set a width of 32 bytes (256-bits), which is four times that 285 # of the default bus. The clock of the CPU is inherited by 286 # default. 287 self.toL2Bus = CoherentBus(width = 32) |
| 288 self.connectCachedPorts(self.toL2Bus) 289 self.l2cache = l2c 290 self.toL2Bus.master = self.l2cache.cpu_side 291 self._cached_ports = ['l2cache.mem_side'] 292 293 def createThreads(self): 294 self.isa = [ isa_class() for i in xrange(self.numThreads) ] 295 if self.checker != NULL: 296 self.checker.createThreads() 297 298 def addCheckerCpu(self): 299 pass | 288 self.connectCachedPorts(self.toL2Bus) 289 self.l2cache = l2c 290 self.toL2Bus.master = self.l2cache.cpu_side 291 self._cached_ports = ['l2cache.mem_side'] 292 293 def createThreads(self): 294 self.isa = [ isa_class() for i in xrange(self.numThreads) ] 295 if self.checker != NULL: 296 self.checker.createThreads() 297 298 def addCheckerCpu(self): 299 pass |