BaseCPU.py (9446:644f2a2c9bfc) BaseCPU.py (9480:d059f8a95a42)
1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 37 unchanged lines hidden (view full) ---

46from m5.defines import buildEnv
47from m5.params import *
48from m5.proxy import *
49
50from Bus import CoherentBus
51from InstTracer import InstTracer
52from ExeTracer import ExeTracer
53from MemObject import MemObject
1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 37 unchanged lines hidden (view full) ---

46from m5.defines import buildEnv
47from m5.params import *
48from m5.proxy import *
49
50from Bus import CoherentBus
51from InstTracer import InstTracer
52from ExeTracer import ExeTracer
53from MemObject import MemObject
54from BranchPredictor import BranchPredictor
54
55default_tracer = ExeTracer()
56
57if buildEnv['TARGET_ISA'] == 'alpha':
58 from AlphaTLB import AlphaDTB, AlphaITB
59 from AlphaInterrupts import AlphaInterrupts
60 from AlphaISA import AlphaISA
61 isa_class = AlphaISA

--- 117 unchanged lines hidden (view full) ---

179 "between CPU models)")
180
181 tracer = Param.InstTracer(default_tracer, "Instruction tracer")
182
183 icache_port = MasterPort("Instruction Port")
184 dcache_port = MasterPort("Data Port")
185 _cached_ports = ['icache_port', 'dcache_port']
186
55
56default_tracer = ExeTracer()
57
58if buildEnv['TARGET_ISA'] == 'alpha':
59 from AlphaTLB import AlphaDTB, AlphaITB
60 from AlphaInterrupts import AlphaInterrupts
61 from AlphaISA import AlphaISA
62 isa_class = AlphaISA

--- 117 unchanged lines hidden (view full) ---

180 "between CPU models)")
181
182 tracer = Param.InstTracer(default_tracer, "Instruction tracer")
183
184 icache_port = MasterPort("Instruction Port")
185 dcache_port = MasterPort("Data Port")
186 _cached_ports = ['icache_port', 'dcache_port']
187
188 branchPred = Param.BranchPredictor(NULL, "Branch Predictor")
189
187 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
188 _cached_ports += ["itb.walker.port", "dtb.walker.port"]
189
190 _uncached_slave_ports = []
191 _uncached_master_ports = []
192 if buildEnv['TARGET_ISA'] == 'x86':
193 _uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"]
194 _uncached_master_ports += ["interrupts.int_master"]

--- 77 unchanged lines hidden --- 		190 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
191 _cached_ports += ["itb.walker.port", "dtb.walker.port"]
192
193 _uncached_slave_ports = []
194 _uncached_master_ports = []
195 if buildEnv['TARGET_ISA'] == 'x86':
196 _uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"]
197 _uncached_master_ports += ["interrupts.int_master"]

--- 77 unchanged lines hidden ---