BaseCPU.py (9338:97b4a2be1e5b) BaseCPU.py (9384:877293183bdf)
1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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52from ExeTracer import ExeTracer
53from MemObject import MemObject
54
55default_tracer = ExeTracer()
56
57if buildEnv['TARGET_ISA'] == 'alpha':
58 from AlphaTLB import AlphaDTB, AlphaITB
59 from AlphaInterrupts import AlphaInterrupts
1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 43 unchanged lines hidden (view full) ---

52from ExeTracer import ExeTracer
53from MemObject import MemObject
54
55default_tracer = ExeTracer()
56
57if buildEnv['TARGET_ISA'] == 'alpha':
58 from AlphaTLB import AlphaDTB, AlphaITB
59 from AlphaInterrupts import AlphaInterrupts
60 from AlphaISA import AlphaISA
61 isa_class = AlphaISA
60elif buildEnv['TARGET_ISA'] == 'sparc':
61 from SparcTLB import SparcTLB
62 from SparcInterrupts import SparcInterrupts
62elif buildEnv['TARGET_ISA'] == 'sparc':
63 from SparcTLB import SparcTLB
64 from SparcInterrupts import SparcInterrupts
65 from SparcISA import SparcISA
66 isa_class = SparcISA
63elif buildEnv['TARGET_ISA'] == 'x86':
64 from X86TLB import X86TLB
65 from X86LocalApic import X86LocalApic
67elif buildEnv['TARGET_ISA'] == 'x86':
68 from X86TLB import X86TLB
69 from X86LocalApic import X86LocalApic
70 from X86ISA import X86ISA
71 isa_class = X86ISA
66elif buildEnv['TARGET_ISA'] == 'mips':
67 from MipsTLB import MipsTLB
68 from MipsInterrupts import MipsInterrupts
72elif buildEnv['TARGET_ISA'] == 'mips':
73 from MipsTLB import MipsTLB
74 from MipsInterrupts import MipsInterrupts
75 from MipsISA import MipsISA
76 isa_class = MipsISA
69elif buildEnv['TARGET_ISA'] == 'arm':
70 from ArmTLB import ArmTLB
71 from ArmInterrupts import ArmInterrupts
77elif buildEnv['TARGET_ISA'] == 'arm':
78 from ArmTLB import ArmTLB
79 from ArmInterrupts import ArmInterrupts
80 from ArmISA import ArmISA
81 isa_class = ArmISA
72elif buildEnv['TARGET_ISA'] == 'power':
73 from PowerTLB import PowerTLB
74 from PowerInterrupts import PowerInterrupts
82elif buildEnv['TARGET_ISA'] == 'power':
83 from PowerTLB import PowerTLB
84 from PowerInterrupts import PowerInterrupts
85 from PowerISA import PowerISA
86 isa_class = PowerISA
75
76class BaseCPU(MemObject):
77 type = 'BaseCPU'
78 abstract = True
79 cxx_header = "cpu/base.hh"
80
81 @classmethod
82 def export_methods(cls, code):

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108
109 workload = VectorParam.Process([], "processes to run")
110
111 if buildEnv['TARGET_ISA'] == 'sparc':
112 dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
113 itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
114 interrupts = Param.SparcInterrupts(
115 NULL, "Interrupt Controller")
87
88class BaseCPU(MemObject):
89 type = 'BaseCPU'
90 abstract = True
91 cxx_header = "cpu/base.hh"
92
93 @classmethod
94 def export_methods(cls, code):

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120
121 workload = VectorParam.Process([], "processes to run")
122
123 if buildEnv['TARGET_ISA'] == 'sparc':
124 dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
125 itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
126 interrupts = Param.SparcInterrupts(
127 NULL, "Interrupt Controller")
128 isa = VectorParam.SparcISA([ isa_class() ], "ISA instance")
116 elif buildEnv['TARGET_ISA'] == 'alpha':
117 dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
118 itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
119 interrupts = Param.AlphaInterrupts(
120 NULL, "Interrupt Controller")
129 elif buildEnv['TARGET_ISA'] == 'alpha':
130 dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
131 itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
132 interrupts = Param.AlphaInterrupts(
133 NULL, "Interrupt Controller")
134 isa = VectorParam.AlphaISA([ isa_class() ], "ISA instance")
121 elif buildEnv['TARGET_ISA'] == 'x86':
122 dtb = Param.X86TLB(X86TLB(), "Data TLB")
123 itb = Param.X86TLB(X86TLB(), "Instruction TLB")
124 interrupts = Param.X86LocalApic(NULL, "Interrupt Controller")
135 elif buildEnv['TARGET_ISA'] == 'x86':
136 dtb = Param.X86TLB(X86TLB(), "Data TLB")
137 itb = Param.X86TLB(X86TLB(), "Instruction TLB")
138 interrupts = Param.X86LocalApic(NULL, "Interrupt Controller")
139 isa = VectorParam.X86ISA([ isa_class() ], "ISA instance")
125 elif buildEnv['TARGET_ISA'] == 'mips':
126 dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
127 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
128 interrupts = Param.MipsInterrupts(
129 NULL, "Interrupt Controller")
140 elif buildEnv['TARGET_ISA'] == 'mips':
141 dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
142 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
143 interrupts = Param.MipsInterrupts(
144 NULL, "Interrupt Controller")
145 isa = VectorParam.MipsISA([ isa_class() ], "ISA instance")
130 elif buildEnv['TARGET_ISA'] == 'arm':
131 dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
132 itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
133 interrupts = Param.ArmInterrupts(
134 NULL, "Interrupt Controller")
146 elif buildEnv['TARGET_ISA'] == 'arm':
147 dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
148 itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
149 interrupts = Param.ArmInterrupts(
150 NULL, "Interrupt Controller")
151 isa = VectorParam.ArmISA([ isa_class() ], "ISA instance")
135 elif buildEnv['TARGET_ISA'] == 'power':
136 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
137 dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
138 itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
139 interrupts = Param.PowerInterrupts(
140 NULL, "Interrupt Controller")
152 elif buildEnv['TARGET_ISA'] == 'power':
153 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
154 dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
155 itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
156 interrupts = Param.PowerInterrupts(
157 NULL, "Interrupt Controller")
158 isa = VectorParam.PowerISA([ isa_class() ], "ISA instance")
141 else:
142 print "Don't know what TLB to use for ISA %s" % \
143 buildEnv['TARGET_ISA']
144 sys.exit(1)
145
146 max_insts_all_threads = Param.Counter(0,
147 "terminate when all threads have reached this inst count")
148 max_insts_any_thread = Param.Counter(0,

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236 # clock for the L1-to-L2 bus, and also set a width of 32 bytes
237 # (256-bits), which is four times that of the default bus.
238 self.toL2Bus = CoherentBus(clock = Parent.clock, width = 32)
239 self.connectCachedPorts(self.toL2Bus)
240 self.l2cache = l2c
241 self.toL2Bus.master = self.l2cache.cpu_side
242 self._cached_ports = ['l2cache.mem_side']
243
159 else:
160 print "Don't know what TLB to use for ISA %s" % \
161 buildEnv['TARGET_ISA']
162 sys.exit(1)
163
164 max_insts_all_threads = Param.Counter(0,
165 "terminate when all threads have reached this inst count")
166 max_insts_any_thread = Param.Counter(0,

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254 # clock for the L1-to-L2 bus, and also set a width of 32 bytes
255 # (256-bits), which is four times that of the default bus.
256 self.toL2Bus = CoherentBus(clock = Parent.clock, width = 32)
257 self.connectCachedPorts(self.toL2Bus)
258 self.l2cache = l2c
259 self.toL2Bus.master = self.l2cache.cpu_side
260 self._cached_ports = ['l2cache.mem_side']
261
262 def createThreads(self):
263 self.isa = [ isa_class() for i in xrange(self.numThreads) ]
264 if self.checker != NULL:
265 self.checker.createThreads()
266
244 def addCheckerCpu(self):
245 pass
267 def addCheckerCpu(self):
268 pass