| BaseCPU.py (9254:f1b35c618252) | BaseCPU.py (9284:f4ff625eae56) |
|---|---|
| 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 222 unchanged lines hidden (view full) --- 231 # Checker doesn't need its own tlb caches because it does 232 # functional accesses only 233 if self.checker != NULL: 234 self._cached_ports += ["checker.itb.walker.port", \ 235 "checker.dtb.walker.port"] 236 237 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 238 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) | 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 222 unchanged lines hidden (view full) --- 231 # Checker doesn't need its own tlb caches because it does 232 # functional accesses only 233 if self.checker != NULL: 234 self._cached_ports += ["checker.itb.walker.port", \ 235 "checker.dtb.walker.port"] 236 237 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 238 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) |
| 239 self.toL2Bus = CoherentBus() | 239 # Override the default bus clock of 1 GHz and uses the CPU 240 # clock for the L1-to-L2 bus, and also set a width of 32 bytes 241 # (256-bits), which is four times that of the default bus. 242 self.toL2Bus = CoherentBus(clock = Parent.clock, width = 32) |
| 240 self.connectCachedPorts(self.toL2Bus) 241 self.l2cache = l2c 242 self.toL2Bus.master = self.l2cache.cpu_side 243 self._cached_ports = ['l2cache.mem_side'] 244 245 def addCheckerCpu(self): 246 pass | 243 self.connectCachedPorts(self.toL2Bus) 244 self.l2cache = l2c 245 self.toL2Bus.master = self.l2cache.cpu_side 246 self._cached_ports = ['l2cache.mem_side'] 247 248 def addCheckerCpu(self): 249 pass |