| BaseCPU.py (9036:6385cf85bf12) | BaseCPU.py (9157:e0bad9d7bbd6) |
|---|---|
| 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 131 unchanged lines hidden (view full) --- 140 max_loads_any_thread = Param.Counter(0, 141 "terminate when any thread reaches this load count") 142 progress_interval = Param.Tick(0, 143 "interval to print out the progress message") 144 145 defer_registration = Param.Bool(False, 146 "defer registration with system (for sampling)") 147 | 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 131 unchanged lines hidden (view full) --- 140 max_loads_any_thread = Param.Counter(0, 141 "terminate when any thread reaches this load count") 142 progress_interval = Param.Tick(0, 143 "interval to print out the progress message") 144 145 defer_registration = Param.Bool(False, 146 "defer registration with system (for sampling)") 147 |
| 148 clock = Param.Clock('1t', "clock speed") 149 phase = Param.Latency('0ns', "clock phase") 150 | |
| 151 tracer = Param.InstTracer(default_tracer, "Instruction tracer") 152 153 icache_port = MasterPort("Instruction Port") 154 dcache_port = MasterPort("Data Port") 155 _cached_ports = ['icache_port', 'dcache_port'] 156 157 if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 158 _cached_ports += ["itb.walker.port", "dtb.walker.port"] --- 75 unchanged lines hidden --- | 148 tracer = Param.InstTracer(default_tracer, "Instruction tracer") 149 150 icache_port = MasterPort("Instruction Port") 151 dcache_port = MasterPort("Data Port") 152 _cached_ports = ['icache_port', 'dcache_port'] 153 154 if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 155 _cached_ports += ["itb.walker.port", "dtb.walker.port"] --- 75 unchanged lines hidden --- |