| BaseCPU.py (8887:20ea02da9c53) | BaseCPU.py (9036:6385cf85bf12) |
|---|---|
| 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 33 unchanged lines hidden (view full) --- 42# Andreas Hansson 43 44import sys 45 46from m5.defines import buildEnv 47from m5.params import * 48from m5.proxy import * 49 | 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 33 unchanged lines hidden (view full) --- 42# Andreas Hansson 43 44import sys 45 46from m5.defines import buildEnv 47from m5.params import * 48from m5.proxy import * 49 |
| 50from Bus import Bus | 50from Bus import CoherentBus |
| 51from InstTracer import InstTracer 52from ExeTracer import ExeTracer 53from MemObject import MemObject 54 55default_tracer = ExeTracer() 56 57if buildEnv['TARGET_ISA'] == 'alpha': 58 from AlphaTLB import AlphaDTB, AlphaITB --- 159 unchanged lines hidden (view full) --- 218 # Checker doesn't need its own tlb caches because it does 219 # functional accesses only 220 if self.checker != NULL: 221 self._cached_ports += ["checker.itb.walker.port", \ 222 "checker.dtb.walker.port"] 223 224 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 225 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) | 51from InstTracer import InstTracer 52from ExeTracer import ExeTracer 53from MemObject import MemObject 54 55default_tracer = ExeTracer() 56 57if buildEnv['TARGET_ISA'] == 'alpha': 58 from AlphaTLB import AlphaDTB, AlphaITB --- 159 unchanged lines hidden (view full) --- 218 # Checker doesn't need its own tlb caches because it does 219 # functional accesses only 220 if self.checker != NULL: 221 self._cached_ports += ["checker.itb.walker.port", \ 222 "checker.dtb.walker.port"] 223 224 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 225 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) |
| 226 self.toL2Bus = Bus() | 226 self.toL2Bus = CoherentBus() |
| 227 self.connectCachedPorts(self.toL2Bus) 228 self.l2cache = l2c 229 self.toL2Bus.master = self.l2cache.cpu_side 230 self._cached_ports = ['l2cache.mem_side'] 231 232 def addCheckerCpu(self): 233 pass | 227 self.connectCachedPorts(self.toL2Bus) 228 self.l2cache = l2c 229 self.toL2Bus.master = self.l2cache.cpu_side 230 self._cached_ports = ['l2cache.mem_side'] 231 232 def addCheckerCpu(self): 233 pass |